High-Performance Ultrasonic Levitation with FPGA-based Phased Arrays

We present a flexible and self-contained platform for acoustic levitation research based on the Xilinx Zynq SoC using an array of ultrasonic emitters. The platform employs an inexpensive ZedBoard and provides fast movement of the levitated objects as well as object detection based on the produced echo. Several features available in the Zynq device are of benefit for this platform: hardware acceleration for the phase calculations, large number of parallel I/Os connected through the FPGA Mezzanine connector (FMC), integrated ADC capabilities to capture echo signals and ease of programmability due to a C-based design flow for both CPU and FPGA. A planar and spherical cap phased arrays are created and we investigate the capabilities and limitations of the different designs to improve the stability of the levitation process.

💡 Research Summary

This paper presents a low‑cost, high‑performance platform for acoustic levitation research built around the Xilinx Zynq‑7000 System‑on‑Chip (SoC) and an inexpensive ZedBoard development kit. The authors integrate a 64‑channel ultrasonic phased‑array (8 × 8 transducer layout) directly with the Zynq device via a Samtec FMC connector, using 68 single‑ended I/Os to drive the array and two additional ADC channels to capture echo signals. The platform exploits three key Zynq features: (1) hardware acceleration of phase‑delay calculations in programmable logic, (2) abundant parallel I/O through the FMC, and (3) on‑chip mixed‑signal capability (integrated ADC) for closed‑loop object detection.

The software running on the ARM Cortex‑A9 processor provides a simple user interface for specifying a 3‑D focal point. When a target coordinate is entered, the processor invokes a custom accelerator implemented in the FPGA fabric using SDSoC/HLS. The accelerator receives the target coordinates and the fixed positions of each transducer, computes the Euclidean distance, divides by the acoustic wavelength, and multiplies by 2π to obtain the required phase shift (expressed as a number of clock cycles). Loop unrolling, pipelining, and optional replication of compute units yield a speed‑up of 2.7× for a single compute unit (64‑transducer frame) and up to 21× when four compute units process a batch of 160 frames. This reduces the phase‑calculation latency from 154 µs to 60 µs and raises the refresh rate from 6.49 kHz to 16.6 kHz, enabling rapid repositioning of levitated objects.

Because the ZedBoard’s 3.3 V I/O cannot directly drive the piezoelectric transducers, each channel is amplified by a TC4427A dual MOSFET driver, stepping the control signal up to 0‑16 V, which matches the voltage rating of the MCUSD16P40B12R (40 kHz) and 250ST180 (25 kHz) transducers used. The authors deliberately drive the transducers with a square wave generated in FPGA logic, avoiding the need for a high‑resolution DAC while still achieving sufficient acoustic pressure.

Temperature variations affect the speed of sound and consequently the wavelength used in phase calculations. To mitigate this, a Pmod HYGRO temperature sensor (14‑bit resolution, ±0.2 °C accuracy) is attached via I²C. The host reads the temperature on demand, updates the speed‑of‑sound value, and recomputes the phase delays, thereby preserving focal accuracy across a typical laboratory temperature range. Experimental data show that without compensation, a 10 °C rise can shift phase delays by several clock cycles and enlarge the focal spot; with compensation, the focal‑point error stays below 5 % of the designed size.

The paper evaluates four array geometries: (a) a flat single‑sided array, (b) a flat array with a reflective plate, (c) a single‑sided spherical‑cap array, and (d) a double‑sided spherical‑cap array. The reflective plate creates a standing wave, doubling acoustic pressure at antinodes and providing stable levitation (nodes become trapping points). Removing the plate reduces pressure and destabilizes the trap. The spherical‑cap configurations naturally focus energy more efficiently, offering superior stability, but require careful mechanical separation between transducers and driver electronics.

Power measurements on a ZC702 evaluation board (which includes power‑management bus monitoring) indicate that the Cortex‑A9 core consumes roughly 700 mW (VCCINT) while the FPGA fabric consumes about 520 mW (VCCINT). The hardware accelerator is therefore more energy‑efficient than a pure software implementation, and the overall system remains well under 2 W, a fraction of the tens of watts typical for commercial levitation rigs.

Cost analysis highlights the stark contrast with existing solutions: commercial platforms often exceed US $20 k, whereas the presented system, comprising a ZedBoard, MOSFET drivers, a PCB, and off‑the‑shelf transducers, totals under US $300. All design files (schematics, PCB layout, HDL source, and software) are released as open source to encourage further research and educational use.

In conclusion, the authors demonstrate that a modest Zynq‑SoC board can serve as a fully self‑contained acoustic levitation platform. By integrating real‑time phase‑calculation acceleration, temperature‑compensated wave synthesis, and mixed‑signal echo detection, the system achieves fast, stable levitation with multi‑point capability while maintaining low power consumption and a very low bill‑of‑materials. The work opens the door to more advanced experiments such as simultaneous multi‑focus levitation, three‑dimensional particle tracking, and hybrid acoustic‑optical manipulation, all built on an accessible, open‑source hardware foundation.