Artificial Retina Using A Hybrid Neural Network With Spatial Transform Capability

This paper covers the design and programming of a hybrid (digital/analog) neural network to function as an artificial retina with the ability to perform a spatial discrete cosine transform. We describe the structure of the circuit, which uses an analog cell that is interlinked using a programmable digital array. The paper is broken into three main parts. First, we present the results of a Matlab simulation. Then we show the circuit simulation in Spice. This is followed by a demonstration of the practical device. This system has intentionally separated components with the specialty analog circuits being separated from the readily available digital field programmable gate array (FPGA) components. Further development includes the use of rapid manufacture-able organic electronics used for the analog components. The planned uses for this platform include crowd development of software that uses the underlying pulse based processing. The development package will include simulators in the form of Matlab and Spice type software platforms.

💡 Research Summary

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The paper presents a hybrid digital‑analog neural network designed to act as an artificial retina capable of performing a spatial discrete cosine transform (DCT). The authors combine analog neuromorphic cells that generate pulse‑rate signals proportional to light intensity with a programmable field‑programmable gate array (FPGA) that scans, weights, and integrates these pulses. The architecture consists of an 8 × 8 × 3 layered network: the first layer converts optical intensity into pulse rates, the second layer executes a one‑dimensional DCT across rows, and the third layer performs a one‑dimensional DCT across columns, yielding a full 2‑D DCT encoded as variable‑rate pulses.

Key technical contributions include:

1. Time‑on encoding – each synapse’s effect is represented by the total “on‑time” derived from the weighted sum of incoming pulses. This converts pulse‑rate information into an analog current that is turned off after the prescribed duration.
2. Hybrid interconnect – analog cells are scanned at >1 MHz, their pulse events stored in a register, and then multiplied by programmable weights stored in FPGA RAM. A destination‑delay table accumulates weighted contributions, allowing for complex (weight + delay) synaptic connections.
3. Two implementation paths – (a) a true hybrid where external analog cells are interfaced with the FPGA, and (b) a fully digital emulation where the analog cell behavior is modeled inside the FPGA. Both parallel and serial processing variants are explored. Parallel processing completes the full weighted‑sum calculation in 64 cycles (≈82 µs), while the serial version needs 4096 cycles, leading to a longer latency (up to 246 µs).
4. Simulation and validation – Matlab simulations (using a Runge‑Kutta model of the analog cell) demonstrate correct DCT output for several test patterns. SPICE simulations verify the analog cell’s membrane potential dynamics and the overall circuit behavior. Hardware prototypes confirm the functional schematics and provide resource‑usage tables (logic elements, registers, pins, memory) for both hybrid and fully digital designs.
5. Performance analysis – Monte‑Carlo timing simulations on 10 000 input variations show a maximum delay spread of 0.1 % error and a decay rate of ~10 %/ms for the analog cell, which is negligible compared with biological firing rates (10 Hz–1 kHz). The authors note that with a nominal 10 Hz firing rate, a single pulse‑train encoding yields a theoretical accuracy of about 10 % over a one‑second evaluation window.

The paper also discusses learning, noting that most learning algorithms would be implemented in the digital domain; a normalized Hebbian rule was tested, but the DCT weight matrix remains hard‑wired. Future work envisions using rapidly manufacturable organic electronics for the analog cells and encouraging crowd‑sourced software development around the pulse‑based processing platform.

Critical assessment:
While the hybrid concept and the time‑on encoding are novel, the manuscript lacks quantitative benchmarks on power consumption, noise robustness, and scalability beyond the 8 × 8 prototype. The reliance on FPGA resources (logic elements scaling quadratically with neuron count) may limit large‑scale deployment. Moreover, the DCT functionality is essentially fixed; extending the architecture to more flexible vision tasks would require dynamic reconfiguration of the weight matrix, which is not demonstrated. The discussion of organic electronics is speculative without experimental data. Nonetheless, the work provides a valuable proof‑of‑concept for integrating analog neuromorphic dynamics with digital control, and it could serve as a stepping stone toward low‑power, edge‑computing visual sensors or neuro‑prosthetic devices if the identified limitations are addressed.