Synthesis of Majority Expressions through Primitive Function Manipulation

Due to technology advancements and circuits miniaturization, the study of logic systems that can be applied to nanotechnology has been progressing steadily. Among the creation of nanoeletronic circuits reversible and majority logic stand out. This paper proposes the MPC (Majority Primitives Combination) algorithm, used for majority logic synthesis. The algorithm receives a truth table as input and returns a majority function that covers the same set of minterms. The formulation of a valid output function is made with the combination of previously optimized functions. As cost criteria the algorithm searches for a function with the least number of levels, followed by the least number of gates, inverters, and gate inputs. In this paper it’s also presented a comparison between the MPC and the exact_mig, currently considered the best algorithm for majority synthesis. The exact_mig encode the exact synthesis of majority functions using the number of levels and gates as cost criteria. The MPC considers two additional cost criteria, the number of inverters and the number of gate inputs, with the goal to further improve exact_mig results. Tests have shown that both algorithms return optimal solutions for all functions with 3 input variables. For functions with 4 inputs, the MPC is able to further improve 42,987 (66%) functions and achieves equal results for 7,198 (11%). For functions with 5 input variables, out of a sample of 1,000 randomly generated functions, the MPC further improved 477 (48%) functions and achieved equal results for 112 (11%).

💡 Research Summary

The paper addresses the growing interest in majority‑based logic for nanoscale electronic circuits and proposes a new synthesis method called the Majority Primitives Combination (MPC) algorithm. MPC takes as input a Boolean truth table with n variables and outputs a majority‑logic network that implements exactly the same set of minterms. The algorithm proceeds in several stages. First, it constructs a primitive‑function library from four categories: constants (C), single‑variable literals (V), single‑gate AND/OR functions (G), and single‑gate majority functions (T). Each primitive is pre‑optimized according to a cost hierarchy that prioritizes the number of logic levels, then the total gate count, followed by the number of inverters and the total number of gate inputs.
Second, MPC exhaustively enumerates all possible two‑level majority expressions by pairing primitives, storing the results in a lookup table called M2. For every distinct minterm set, M2 retains only the cheapest expression, guaranteeing that any function covered by a two‑level majority network is represented by an optimal solution. Because all 3‑input Boolean functions (256 in total) are either primitives (40) or covered by M2 (216), MPC always returns the optimal solution for the 3‑input case.
For 4‑ and 5‑input functions, many functions cannot be expressed with a single primitive or a two‑level expression. MPC therefore applies a two‑loop synthesis. In the first loop it selects a pair of primitives or M2 expressions (X1 and X2) that together cover all required minterms without introducing extraneous ones. It then builds a vector v that records, for each minterm, whether it is covered by none, one, or both of the selected sub‑functions. Positions with coverage 2 or 0 become don’t‑care conditions, and a third sub‑function X3 is synthesized to fill the remaining gaps using Karnaugh‑map‑style minimization or the B2M method. If this loop fails to find a solution, the second loop invokes Shannon decomposition, recursively splitting the target function into two sub‑functions and synthesizing each with MPC. This recursive step can generate three‑ or four‑level majority networks when necessary.
A key contribution is the explicit handling of inverter count via the Ω.I (Inverter Propagation) axiom of majority algebra. By exploiting the self‑dual property of the majority operator, MPC can often replace an output inverter with an input inverter, reducing the overall inverter budget. The algorithm also pre‑defines four inverter patterns for single‑gate majority functions, enabling fast cost evaluation.
Experimental results show that MPC matches exact_mig (the state‑of‑the‑art exact synthesis tool) on all 3‑input functions, improves 66 % of the 4‑input functions while matching 11 %, and for a random sample of 1 000 five‑input functions improves 48 % and matches 11 %. Improvements are measured across all four cost dimensions (levels, gates, inverters, inputs), demonstrating that the additional cost criteria lead to genuinely more efficient circuits. The paper also discusses the scalability of the primitive and M2 tables, noting that they are stored as LUTs for fast lookup, and that the synthesis time remains practical for up to five inputs.
In conclusion, the MPC algorithm extends exact majority synthesis by incorporating inverter and input‑pin costs into the optimization objective, achieving better trade‑offs in area, power, and delay for a large fraction of Boolean functions. The authors suggest future work on extending the method to six or more inputs, integrating technology‑aware cost models, and exploring automated placement and routing of the resulting majority networks.