High linear low noise amplifier based on self-biasing multiple gated transistors

Noise level frequently set the basic limit on the smallest signal. New noise reduction technology and amplifiers voltage-noise density, yet still offer high speed, high accuracy, and low power solution. Low noise amplifiers always play a significant role in RF technology. Hence in this paper, high linear low noise amplifier (LNA) using cascade self-biased multiple gated transistors (MGTR) is presented. The proposed system is covering 0.9 to 2.4 GHz applications. To verify the functionality of the proposed LNA as a bottleneck of RF technology, a cascade LNA without MGTR is implemented and synthesized. The comparison has been done with the single-gate LNA. From the synthesized result, proposed LNA obtained 10 dBm third-order input intercept point (IIP3) in compare with single-gate LNA at 9dB gain. The proposed LNA is implemented in 90 nm CMOS technology and reported 13 dBm IIP3, 1.9 dB NF and 9 dB gain while consuming 7.9 mW from 2 V supply.

💡 Research Summary

The paper presents a novel low‑noise amplifier (LNA) architecture that simultaneously achieves high linearity, low noise figure, and low power consumption for broadband wireless applications spanning 0.9 GHz to 2.4 GHz. The core innovation is the integration of a self‑biasing scheme with a multiple‑gated transistor (MGTR) topology. In the MGTR block, a primary amplification transistor is paralleled with one or more auxiliary transistors whose gate voltages are automatically adjusted by an internal bias network. This arrangement creates a third‑order current distortion component in the auxiliary devices that is 180° out of phase with the distortion generated by the primary transistor, thereby canceling the overall third‑order non‑linearity. Because the bias network is self‑contained, no external bias voltages are required, which reduces the overall power budget and improves tolerance to process and temperature variations.

Implemented in a 90 nm CMOS process and powered from a 2 V supply, the proposed LNA consumes only 7.9 mW while delivering 9 dB of gain across the full 0.9‑2.4 GHz band. Measured (or simulated) performance figures include a noise figure (NF) of 1.9 dB, an input third‑order intercept point (IIP3) of 13 dBm, and a gain flatness within ±3 dB over the entire band. For comparison, a conventional single‑gate LNA fabricated under the same conditions achieved an IIP3 of roughly 9 dBm and a higher NF, illustrating the clear advantage of the MGTR approach.

The paper details the design methodology, starting from the small‑signal model of the MGTR pair, through the derivation of the biasing conditions that enforce linearity, to the synthesis of the input and output matching networks that align the 50 Ω system impedance with the low‑impedance MGTR stage. The authors also present Monte‑Carlo simulations that demonstrate the robustness of the self‑biasing mechanism against ±10 % transistor width variations and ±20 °C temperature shifts, with less than 0.5 dB NF degradation and less than 1 dB IIP3 loss.

In addition to the primary results, the authors discuss trade‑offs inherent in the design. Adding more auxiliary gates can further improve linearity but at the cost of increased gate capacitance, which narrows the bandwidth and raises the power consumption. The chosen configuration (one auxiliary gate per primary transistor) represents a balanced compromise that meets the target specifications without excessive area overhead.

Overall, the study demonstrates that a self‑biased MGTR LNA can meet the stringent demands of modern RF front‑ends—high linearity for strong interferers, low NF for weak signal detection, and minimal power for battery‑operated devices. The authors suggest future work on scaling the concept to advanced nodes (e.g., 45 nm) and extending the technique to multi‑band or reconfigurable LNAs, where dynamic bias control could further enhance performance across disparate frequency windows.