A Design of FPGA Based Small Animal PET Real Time Digital Signal Processing and Correction Logic

Small animal Positron Emission Tomography (PET) is dedicated to small animal imaging. Animals used in experiments, such as rats and monkeys, are often much smaller than human bodies, which requires higher position and energy precision of the PET imaging system. Besides, Flexibility, high efficiency are also the major demands of a practical PET system. These requires a high-quality analog front-end and a digital signal processing logic with high efficiency and compatibility of multiple data processing modes. The digital signal processing logic of the small animal PET system presented in this paper implements 32-channel signal processing in a single Xilinx Artix-7 family of Field-Programmable Gate Array (FPGA). The logic is designed to support three online modes which are regular package mode, flood map and energy spectrum histogram. Several functions are integrated, including two-dimensional (2D) raw position calculation, crystal identification, events filtering, etc. Besides, a series of online corrections are also integrated, such as photon peak correction to 511 keV and timing offset correction with crystal granularity. A Gigabit Ethernet interface is utilized for data transfer, Look-Up Tables (LUTs) configuration and commands issuing. The pipe-line logic processes the signals at 125 MHz with a rate of 1,000,000 events/s. A series of initial tests are conducted. The results indicate that the digital processing logic achieves the expectations.

💡 Research Summary

This paper presents a comprehensive design of a digital signal processing (DSP) logic for a small‑animal Positron Emission Tomography (PET) system, implemented on a single Xilinx Artix‑7 FPGA. The system processes 32 detector channels (eight SiPM signals per detector block, dual‑ended readout) and supports three online operating modes: regular package mode, flood‑map histogram mode, and energy‑spectrum histogram mode.

In regular package mode, the eight area‑integrated signals from the analog front‑end are used to compute a 2‑D raw position (x, y) and depth‑of‑interaction (DOI) via a center‑of‑gravity algorithm. The raw position is mapped to a crystal identifier using a Crystal Look‑Up Table (CLT). Energy is obtained by summing the eight signals and applying a photon‑peak LUT to correct each crystal’s response to the 511 keV photopeak. Timing information from an on‑chip Time‑to‑Digital Converter (TDC) is corrected with a crystal‑specific offset LUT. Events are filtered by a preset energy window before being packaged for transmission.

Flood‑map and energy‑spectrum histogram modes generate 2‑D position histograms (512 × 512) and per‑crystal energy spectra (23 × 23 × 256 depth), respectively. Both modes can operate online, using block RAM inside the FPGA to accumulate counts, or offline, where raw (x, y) or energy data are streamed to a host PC for post‑processing. A token‑ring arbitration scheme ensures that the four detector‑block FIFOs are read without overflow, even when event rates are non‑uniform across blocks.

A major challenge addressed in the work is the FPGA’s limited Block RAM. The naïve implementation of the CLT would require roughly 10 Mb per four blocks, and together with the two histograms and other LUTs would exceed the available resources. The authors introduce a “boundary CLT” technique: the original 2‑D CLT is decomposed into two 1‑D boundary tables (one for x, one for y). Each boundary table stores 22 boundary values per line, each 9 bits wide, resulting in a memory footprint of only 0.19 Mb per block. This reduces total LUT and histogram memory usage from 25.29 Mb to 10.89 Mb, allowing the entire design to fit within the Artix‑7 device without external memory.

Data communication between the Singles Processing Unit (SPU) and the host PC is realized via a Gigabit Ethernet link. Commands, LUT updates, and configuration data are sent from the PC to the SPU, while processed event packets are streamed back. The Ethernet interface also carries the histogram data when operating in offline mode.

Performance evaluation assumes a maximum source activity of 200 µCi (7.4 MBq), yielding up to 14.8 M singles per second for the whole scanner. With an 80 % detection efficiency, each SPU is expected to handle about 4.8 M events per second. The implemented pipeline runs at 125 MHz and achieves a sustained processing rate of 1 MHz events, meeting the design goal. Experimental tests confirm correct operation of position calculation, crystal identification, energy and timing corrections, and histogram generation.

In conclusion, the paper demonstrates that a single mid‑range FPGA can integrate high‑throughput, multi‑mode signal processing for a small‑animal PET system while maintaining flexibility through programmable LUTs and online/offline histogram modes. The boundary CLT method provides a scalable solution to memory constraints, and the token‑ring data flow architecture ensures robust handling of bursty event streams. Future work may explore multi‑FPGA scaling, tighter integration with coincidence processing, and real‑time image reconstruction pipelines.