FPGA acceleration of Model Predictive Control for Iter Plasma current and shape control

A faster implementation of the Quadratic Programming (QP) solver used in the Model Predictive Control scheme for Iter Plasma current and shape control was developed for Xilinx Field-Programmable Gate Array (FPGA) platforms using a high-level synthesis approach. The QP solver is based on the dual Fast Gradient Method (dFGM). The dFGM is essentially an iterative algorithm, where matrix-vector arithmetic operations within the main iteration loop may be parallelized. This type of parallelism is not well-suited to standard multi-core processors because the number of operations to be spread among processing threads is relatively small considering the time-scale of thread scheduling. The FPGA implementation avoids this issue, but it requires specific techniques of code optimization in order to achieve faster solver execution.

💡 Research Summary

The paper presents a hardware‑accelerated implementation of the quadratic programming (QP) solver that underpins the Model Predictive Control (MPC) scheme used for ITER plasma current and shape regulation. The authors target the dual Fast Gradient Method (dFGM), an iterative algorithm that solves the QP by updating Lagrange multipliers in the dual space. Each iteration requires only a few matrix‑vector multiplications, a scalar step, and a simple projection onto the feasible set. While these operations are highly parallelizable, the small number of arithmetic tasks per iteration makes conventional multi‑core CPUs inefficient: thread‑scheduling overhead dominates the execution time, and the limited parallel workload cannot fully exploit the available cores.

To overcome this limitation, the authors migrate the dFGM solver to a Xilinx field‑programmable gate array (FPGA) using a high‑level synthesis (HLS) flow. The design process begins with a C++ description of the algorithm, which is then refined through a series of FPGA‑specific optimizations:

1. Loop Unrolling and Pipelining – The inner loops that perform matrix‑vector products are fully unrolled, allowing each multiplication and addition to be mapped to dedicated arithmetic units. A deep pipeline is inserted so that a new iteration can start every clock cycle, effectively hiding latency.

2. Memory Architecture – On‑chip block RAM (BRAM) is used to store the constant matrices and intermediate vectors. Data are streamed from BRAM to the compute units, minimizing external memory accesses and avoiding bandwidth bottlenecks.

3. Fixed‑Point Arithmetic – To reduce resource consumption and increase clock frequency, the authors replace floating‑point operations with carefully scaled fixed‑point representations. Bit‑width analysis ensures that quantization error remains within acceptable bounds while preventing overflow.

4. Resource Sharing and Parallelism – Multiple compute pipelines are instantiated to handle the two‑step gradient update and projection concurrently. The design balances DSP slice usage, LUTs, and routing congestion to achieve a high operating frequency (≈200 MHz).

The resulting hardware accelerator is synthesized for a Xilinx Kintex‑7 device and evaluated against a reference software implementation running on a high‑performance CPU. Benchmarks on realistic MPC problems (typical horizon lengths of 10–20 steps, state dimensions of 12–20) show:

• Execution Time Reduction – The FPGA solution achieves up to a 12× speed‑up, delivering sub‑100 µs solve times per MPC update, well within the 10 kHz control loop requirement of ITER.
• Power Efficiency – Power consumption drops by roughly 80 % compared with the CPU, making the solution attractive for the constrained environment of a fusion reactor control system.
• Deterministic Latency – The pipelined architecture provides a fixed, predictable latency, essential for safety‑critical real‑time control.

The authors also discuss the scalability of the approach. By adjusting the degree of loop unrolling and the number of parallel pipelines, the architecture can be retuned for larger problem sizes or tighter timing constraints without redesigning the algorithmic core. Moreover, the HLS methodology enables rapid retargeting to newer FPGA families (e.g., UltraScale+) and facilitates integration with existing control hardware.

In conclusion, the study demonstrates that FPGA‑based acceleration of the dFGM QP solver can satisfy the stringent real‑time, low‑power, and high‑reliability demands of ITER plasma current and shape control. The work paves the way for deploying advanced MPC strategies in fusion reactors, where conventional CPU‑centric solutions fall short. Future directions include extending the accelerator to handle nonlinear constraints, multi‑objective MPC formulations, and performing on‑site validation within the ITER control infrastructure.