Scanning Test System Prototype of p/sFEB for the ATLAS Phase-I sTGC Trigger Upgrade

Scanning T est System Prototype of p/sFEB for the A TLAS Phase-I sTGC T rigger Upgrade Xinxin W ang, Feng Li, Shengquan Liu, Peng Miao, Zhilei Zhang, T ianru Geng, Shuang Zhou,and Ge Jin Abstract —the Pad Fr ont End Board (pFEB) and the Strip Front End Board (sFEB) ar e developed f or the A TLAS Phase- I sTGC T rigger Upgrade. The pFEB is used to to gather and analyze pads trigger , and the sFEB is developed to accept the pad trigger to define the regions-of-inter est for strips readout. The performance of p/sFEBs must be confirmed bef ore they ar e mounted on the sTGC detector . W e will present the scanning test system prototype which is designed according to the test requir ements of the p/sFEB. In this test system prototype, a simulation signal board is developed to generate different types of signal to the p/sFEB. PC software and FPGA XADC cooperate to achieve the scan test of analog parameter . Index T erms —small-strip thin gap chamber (sTGC) detector , field programmable gate array (FPGA), A utomatic testing, Real- time system. I . I N T RO D U C T I O N A TLAS [1] detector which is one of the four experiments at Large Hadron Collider will fulfill Phase-I upgrade to extend the frontier of particle physics. The upgrade is going to replace the inner detector (Small Wheel, SW) [2] of the end-cap muon spectrometer with the new small wheel detector (NSW), which consists of the Small-strip Thin Gap Chamber (sTGC) [3] and Micromeg as (MM). The small-strip TGC (sTGC) in which the strip pitch is much smaller than that of the current A TLAS TGC will be applied for the NSW upgrade. STGC contains pad, wire and strip readout. The pads are used to identify muon tracks roughly pointing to the interaction point (IP) through a 3-out-of-4 coincidence and define which strips need to be readout to obtain a precise measurement in the bending coordinate for the e vent selection. The Pad Front End Board (pFEB) [4] is de veloped to readout pads signal to gather and analyze pads trigger . The Strip Front End Board (sFEB) [5] is dev eloped to accept the pad trigger to define the regions-of-interest for strips readout. Both of pFEB and sFEB receiv e sTGC signals through the VMM3 [6],[7] ASIC which handles 64 input signals, and outputs the trigger data and raw data of hit ev ents. Manuscript received Feb 9, 2018. This work was supported by the Na- tional Natural Science F oundation of China under Grants 11461141010 and 11375179, and in part by “the Fundamental Research Funds for the Central Univ ersities” under grant No. WK2360000005. Xinxin W ang, Feng Li, Shengquan Liu, Peng Miao, Zhilei Zhang, T ianru Geng, Shuang Zhou, and Ge Jin are with State Key Lab- oratory of Particle Detection and Electronics, University of Science and T echnology of China, Hefei 230026, P .R. of China (phone: +86-18019946174; e-mail: wxx10@mail.ustc.edu.cn,phonelee@ustc.edu.cn, lsqlsq@mail.ustc.edu.cn, mpmp@mail.ustc.edu.cn, zzlei@mail.ustc.edu.cn, gudujian@mail.ustc.edu.cn, neo@mail.ustc.edu.cn, goldjin@ustc.edu.cn ). VMM3 Configuration Ethernet Core FPGA Rx_Data [7..0] Tx_Data [7..0] VMM3_ 1 VMM3_ 2 VMM3_ 3 Daisychain Configuration Data Synchronization andupload D0 D0 D1 D1 D1 D0 PDO1 PDO2 PDO3 Ethernet Chip GFZ Connect o r 30*10 Computer Simulation Signal Board 64 64 64 256 Channels pFEB NetworkCable NetworkCable Fig. 1. Block diagram of T est Prototype System About 2000 p/sFEBs will be produced for final deliv ery and engineering backup. Before the p/sFEB are mounted on the detector , we need to confirm the performance of all the p/sFEBs. According to the function of p/sFEB in the whole system, the performance testing of each p/sFEB includes baseline test, threshold DA C calibration, internal test pulse D A C calibration, gain test and dead channel test, each of which are very important for the front-end electronic system. W e de velop the scanning test system prototype of the p/sFEB. In this test system prototype, a simulation signal board is de veloped to generate dif ferent types of signal to the p/sFEB. PC software and FPGA XADC cooperate to achieve the scan test of analog parameter . The PC software is written based on Qt platform using the standard C++. I I . F U N C T I O N A N D I M P L E M E N TA T I O N A. T est System Pr ototype Har dware Structure Fig.1 is a block diagram of the test system prototype. The p/sFEB includes three/eight VMM3 chips, one Kinte x-7 FPGA for buf fering VMM3 data, one Gigabit Ethernet Transcei ver (GET), and connectors.The VMM3, which consists of 64 linear front-end channels, is an Application Specific Integrated Circuit (ASIC) for the detector . When the p/sFEB is connected to the sTGC detector , the analog signals from the sTGC detector are transmitted through the GFZ connector (10 * 30) to the p/sFEB and then into the three VMM3 chips via the protection circuit. Fig. 2. GUI of T est System Prototype The simulation signal board [8] can be used to provide p/sFEB with 256/512 test pulses via the GFZ connector . In addition, the VMM3 chip can generate an adjustable amplitude test pulse signal internally . The pulse signal is sent to each linear front-end channel of the VMM3. The VMM3 chip outputs digital signal into the FPGA, and the FPGA completes the corresponding readout and analysis works. The FPGA communicates with a computer through the network cable, achieving the VMM3 initialization and data transmission. B. T est System Pr ototype Implementation Each VMM3 chip requires 1728 configuration bits contain- ing polarity , gain, peak time, threshold and other settings. Fig.2 sho ws the Qt-based GUI of the test system. The Qt- based GUI can complete the interaction between the computer and test board, automatic modification of parameters, issued commands and data acquisition. Pcap library is used to get access to Ethernet. In order to make the software run more smoothly and solve the problem of GUI stuck, the software uses a multi-threaded framework so that the data acquisition and user interface are built into different threads. Furthermore, this Qt-based GUI has the function of real-time data collection, analysis and display . This function is very important for p/sFEBs. It is notew orthy that the outputs of 192/512 channels base- line test, threshold DA C calibration test, and internal test pulse D A C calibration test are analog signals. W ithout this automatic test system, an oscilloscope needs to be connected to the p/sFEB to read the analog value. Using an oscilloscope to test is very time-consuming and not easy to take multiple measure- ments on average due to the need of testing many channels. So our system uses XADC in FPGA for automatic scanning to complete these three tests, which can change the configuration bits and sampling by XADC automatically . Finally , the digital data outputs to the computer through the Ethernet, and then achieving the purpose of rapid measurement. I I I . T E S T R E S U LT S Fig.3 is the construction of the test platform. After many tests, it is proved that the test system is reliable and can truly reflect the relev ant characteristics of p/sFEB. W e develop the simulation signal board which can outputs 256 channels Fig. 3. the Construction of T est System Prototype Fig. 4. the real-time result information of VMM3 simulation signals in 6 kinds of mode to provide p/sFEB with 256/512 test pulses via the GFZ connector . The Qt-based GUI will collect the hit event raw data and decode them. Then display the corresponding information. Fig. 4 shows the channel and amplitude test results for all the three VMM3s. In this GUI, the top three graphs displays hit ev ent counts of VMM3 from channel 1 to channel 64, and the bottom three graphs display hits amplitude distribute information of one channel.W e can find dead channels of each VMM3 from these graphs, and then further confirm this through another method to make the result more exactly . For the measurement of analog signals, we build the auto- matic scan test framework using some auxiliary analog inputs of the FPGA XADC. In this way , the analog signals can be measured several times to get the average value, which can increase the reliability and accuracy of the test result. Fig.5 shows the result of baseline scan test of a VMM3 chip. Each channel tests 100 times. From this graph, we can get the consistency and v ariability of the 64 channel baseline so that we can set the threshold of VMM3 chip. I V . C O N C L U S I O N In this paper , we described the scanning test system pro- totype for p/sFEB in detail. In this test system prototype, Fig. 5. Baseline scan result for 64 channels of the VMM3 chip a simulation signal board is dev eloped to generate different types of signals to the p/sFEB. PC software and FPGA XADC cooperate to achiev e the scan test of analog parameter . W ith this system, we can test the circuit board quickly and reliably . In the early upgrade, the scanning test system is used for the p/sFEB performance test. R E F E R E N C E S [1] A. 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