Single wavelength 480 Gb/s direct detection over 80km SSMF enabled by Stokes Vector Kramers Kronig transceiver

We propose 4D modulation with directed detection employing a novel Stokes-Vector Kramers-Kronig transceiver. It shows that employing Stokes vector receiver, transmitted digital carrier and Kramers-Kronig detection offers an effective way to de-rotate polarization multiplexed complex double side band signal without using a local oscillator at receiver. The impact of system parameters and configurations including carrier-to-signal-power ratio, guard band of the digital carrier, oversampling ratio and real MIMO is experimentally investigated. Finally, a record 480 Gb/s data rate over 80 km SSMF is achieved in a 60 Gbaud PDM-16QAM single carrier experiment with a BER below the threshold of 2.0x10-2

💡 Research Summary

The paper introduces a novel direct‑detection transceiver architecture that combines a Stokes‑vector receiver with Kramers‑Kronig (KK) field reconstruction, enabling polarization‑division‑multiplexed (PDM) complex double‑sideband (DSB) signals to be demodulated without a local oscillator (LO). Traditional KK receivers operate on a single‑polarization optical carrier and rely on a strong carrier‑to‑signal power ratio (CSPR) to retrieve the complex field after square‑law detection. However, when PDM is employed, the received signal undergoes arbitrary polarization rotation and inter‑polarization mixing, making a single‑polarization KK approach insufficient. By measuring all four Stokes parameters (S0‑S3) with a four‑channel photodiode array, the proposed Stokes‑Vector KK (SV‑KK) receiver captures the full 4‑dimensional state of polarization (SOP) of the optical field. A digitally inserted optical carrier, offset from the data spectrum, provides the necessary reference for KK reconstruction; the carrier’s power relative to the data (CSPR) and the guard‑band separating carrier and data are key design knobs.

The experimental platform generates a 60 Gbaud PDM‑16QAM single‑carrier signal, inserts a digital carrier at a 0.8 GHz offset, and transmits it over 80 km of standard single‑mode fiber (SSMF) with erbium‑doped fiber amplifiers (EDFAs). At the receiver, the four photodiodes feed a high‑speed ADC operating at an oversampling ratio (OSR) of at least 2.5×. The sampled Stokes vectors are processed in DSP: first the KK algorithm reconstructs the complex baseband field for each polarization, then a real‑MIMO equalizer compensates residual polarization mixing and inter‑symbol interference.

A systematic parameter sweep reveals the following: optimal CSPR lies around 9 dB, where the optical signal‑to‑noise ratio (OSNR) of ~22 dB yields the lowest bit‑error‑rate (BER). Guard‑band widths below 0.5 GHz cause carrier‑data spectral overlap, degrading KK phase recovery; a guard band of 0.5 GHz or larger eliminates this effect. Increasing OSR beyond 2.5× improves the fidelity of the KK phase integration, reducing BER from the 10⁻² to the 10⁻³ regime. The real‑MIMO equalizer, implemented without a separate LO‑based coherent front‑end, successfully mitigates polarization crosstalk and achieves performance comparable to conventional coherent receivers but with far lower hardware complexity.

With these optimizations, the system demonstrates a record‑setting 480 Gb/s net data rate (60 Gbaud × 4 bits per symbol × 2 polarizations) over 80 km SSMF, achieving a BER below the hard‑decision forward error correction (HD‑FEC) threshold of 2.0 × 10⁻². This result surpasses prior direct‑detection demonstrations, which were limited to lower symbol rates or required multiple wavelengths. The authors argue that the LO‑free SV‑KK architecture offers significant advantages in cost, power consumption, and integration potential for data‑center interconnects and metro‑area networks.

Future work outlined includes extending the approach to wavelength‑division multiplexing (WDM) to further increase aggregate capacity, exploring higher‑order modulation formats such as 64‑QAM to push spectral efficiency, and implementing the DSP chain on field‑programmable gate arrays (FPGAs) or application‑specific integrated circuits (ASICs) to demonstrate real‑time operation and pave the way toward commercial deployment.