Automated Formal Equivalence Verification of Pipelined Nested Loops in Datapath Designs

Automated Formal Equivalence Verification of Pipelined Nested Loops in Datapath Designs Payman Behnam, Student Member IEEE, Bijan Alizadeh, Senior Member IEEE, Sajjad Taheri, Student Member IEEE Abstract— The ever-growing complexity of digital systems has made designers move toward using Electronic System Level (ESL) design methodology at a higher abstraction level. The designs at ESL are then automatically synthesized to Register Transfer Level (RTL) by means of High Level or behavioral Synthesis (HLS) tools. Due to possibility of buggy synthesis, especially when the target design must be manipulated or optimized (i.e., pipelining), an efficient equivalence checking method is necessary to check functional equivalency of the ESL specification and the RTL implementation. This problem is even more serious in the case of loop pipelining, since several challenges such as overlapping execution, retiming and forwarding occurre which make traditional sequential equivalence checking approaches, inapplicable. At the same time, the growing market for datapath dominated applications such as DSP for multimedia applications and embedded systems requires a suitable Computer-Aided Design (CAD) support for their verification. In this paper, we present an efficient formal approach to check the equivalence of synthesized RTL against the high-level specification in the presence of pipelining transformations. To increase the scalability of our proposed method, we dynamically divide the designs into several smaller parts called segments by introducing cut-points. Then we employ Modular Horner Expansion Diagram (M-HED) to check whether the specification and implementation are equivalent or not. In an iterative manner, the equivalence checking for each segment is performed. At each step, the equivalent nodes and those nodes which have an impact on them are removed until the whole design is covered. Our proposed method enables us to deal with the equivalence checking problem for behaviorally synthesized designs even in the presence of pipelines for nested loops. The empirical results demonstrate the efficiency and scalability of our proposed method in terms of run-time and memory usage for several large designs synthesized by a commercial behavioral synthesis tool. Average improvements in terms of the memory usage and run time in comparison with SMT- and SAT-based equivalence checking are 16.7× and 111.9×, respectively. Index Terms— Formal verification, equivalence checking, piplined nedted loop, HED —————————— u —————————— 1. INTRODUCTION he complexity of next generation of digital systems has overtaken traditional time consuming handcrafted RTL design methods. Therefore, some approaches are de- sirable to generate RTL codes automatically. High Level Synthesis (HLS) tools have been provided to respond to such needs. The HLS is the process of generating RTL de- sign from higher level programs such as C, C++, SystemC, or so on [6]. Using HLS tools leads to more productive designs for next-generation, computationally intensive applications. When we make use of HLS tools, however, we need to make sure that synthesized RTL is bug free. This indicates that the transformation correctness of high level or behavioral synthesis phase is very important [2, 3]. A large amount of work has been done to verify the RTL against its specification. A combinational equivalence checking approach between designs in SystemC and RTL has been suggested in [4]. The authors of [7], [8] and [9] presented Sequential Equivalence Checking (SEC) ap- proaches between software specification and hardware implementation. During equivalence checking, several optimization techniques such as cut-point, cut-plane and cut-loop are used. The cut-point optimization is to find internal equivalent nodes of specification and their corre- sponding circuit implementations. Cut-points reduce the size of symbolic expressions by replacing verified sub- circuits with new symbolic values [28]. Cut-plane is con- sidered as a set of cut-points while cut-loop is considered as a cut-plane at the end of a loop [30]. Some techniques have been proposed to check the equivalency between combinational circuits with some structural similarities using bit-level decision diagrams [28, 31] SAT-based ap- proaches [38, 39, 43, 44], probabilistic methods [46] and directed test generations [47]. The structural similarities enable them to find identical internal nets as cut-points to partition the whole design into a set of smaller segments. However, their approach to problem of equivalence checking is limited to bit level verification and hence can- not handle large RTL designs. In [30], the authors have proposed a novel approach to verify equivalence of C- based system level description versus RTL model by look- ing for merge-points as early as possible to reduce the size of equivalence checking problems. This method however is suggest

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