BILBO-friendly Hybrid BIST Architecture with Asymmetric Polynomial Reseeding

Keywords-component; BIST; DFT; BILBO; hybrid; reconfigurable; SoC testing I. INTRODUCTION S a result of advances in technology of integrated digital circuits both in size and dimension, more complex and
dense circuits have evolved. Although test and testing strategies have also moderately improved, new challenges introduced by this progress necessitate more improvements in this area. The issue of porting test data to specific cores for complex systems (e.g., SoCs) has become more important due to such improvements. As a system gets larger and more complex, the cost of providing test data for its internal components increases. Build-in self-test (BIST) methods [1, 5] are proposed to mitigate the decrease in efficiency and applicability of off-chip testers. In these methods, a system includes extra components to facilitate the testing process. Multi input signature registers (MISR), pseudo random pattern generators (PRPG), and built-in logic block observer (BILBO) architectures [1, 6, 7] are examples for these units. Random test socket (RTS) is one of the most common BIST architectures that uses chained internal registers for applying test patterns and analyzing test results [7]. Utilizing chained registers increases accessibility and observability of sequential circuits under test (CUT). Thereby as expected, the achieved fault coverage in BIST methods with chained registers is relatively high.
BIST methods usually use three sources for providing their

test data. The first source is using pseudo-random test generation structures like linear feedback shift register (LFSR). Low cost test vectors could be achieved from this source, but as a drawback, the obtained fault coverage is relatively low as compared with deterministic test vectors. The second source is deterministic test data stored in internal memories units of the CUT. Although using this source could lead to high coverage, the cost of dedicating expensive internal memory to the test vectors degrades efficiency of using this source. As the third source, a BIST circuit can provide its test data from an external source. This also has the disadvantage of employing expensive communication infrastructure for the test data which can negatively affect the performance of the system. Many works have been done for improving LFSR based BIST architectures [12-14], LFSR reconfiguration [15], and optimized reseeding [16-18] to get high fault coverage and less test application time. In order to achieve high fault coverage alongside with low test application time, some works [8-11] have attempted to use hybrid BIST methods that include scan based approaches. The work in [19] has proposed a hybrid BIST method which makes use of both internally generated pseudo random test data and test data from external sources. In this work a complete hybrid BIST architecture is proposed which employs a combination of tests from a multistage pseudo random test pattern generation method, and an external deterministic test data set. The proposed hybrid BIST makes an effort to reduce test time by decreasing the number of deterministic test vectors without affecting the overall fault coverage. The rest of this paper is organized as follows: Section II describes proposed BIST architecture. Section III presents a methodology to apply proposed test method. In Section IV, the evaluation method is expressed. Results are illustrated in Section V and finally conclusions are drawn in Section VI. II. PROPOSED ARCHITECTURE Build-in self-test structures facilitate the testing process by integrating some or complete parts of testing components for test generation, test application, and result observation. As a BILBO-friendly Hybrid BIST Architecture with Asymmetric Polynomial Reseeding           and     el_sadredini@comp.iust.ac.ir, mr.najafi

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