Low resistive edge contacts to CVD-grown graphene using a CMOS compatible metal

Low resistive edge contacts to CVD-grown graphene using a CMOS compatible metal

Mehrdad Shaygan 1*, Martin Otto1, Abhay A. Sagade 1,2, Carlos A. Chavarin3,4, Gerd Bacher3, Wolfgang Mertin3, Daniel Neumaier1

*Corresponding Author: E-mail: shaygan@amo.de, m.shaygan@gmail.com

1 Advanced Microelectronic Center Aachen, AMO GmbH, 52074 Aachen, Germany 2 Center for Advanced Photonics and Electronics, Department of Engineering, 9 JJ Thomson Avenue, University of Cambridge, Cambridge CB3 0FA, UK. 3 Werkstoffe der Elektrotechnik, Faculty of Engineering, University Duisburg-Essen, 47057 Duisburg, Germany 4 Innovations for High Performance Microelectronics, IHP GmbH, 15236 Frankfurt (Oder), Germany

The exploitation of the excellent intrinsic electronic properties of graphene for device applications is hampered by a large contact resistance between the metal and graphene. The formation of edge contacts rather than top contacts is one of the most promising solutions for realizing low ohmic contacts. In this paper the fabrication and characterization of edge contacts to large area CVD-grown monolayer graphene by means of optical lithography using CMOS compatible metals, i.e. Nickel and Aluminum is reported. Extraction of the contact resistance by Transfer Line Method (TLM) as well as the direct measurement using Kelvin Probe Force Microscopy demonstrates a very low width specific contact resistance down to 130 Ωµm. The contact resistance is found to be stable for annealing temperatures up to 150°C enabling further device processing. Using this contact scheme for edge contacts, a field effect transistor based on CVD graphene with a high transconductance of 0.63 mS/µm at 1 V bias voltage is fabricated.

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1. Introduction Graphene [1,2] has attracted scientific and technological interest that has been fueled by its unique properties such as high intrinsic mobility [3], high saturation velocity [4] and large breakdown current density [5]. Especially the potential integration of graphene-based electronic and photonic devices into a silicon complementary metal-oxide-semiconductor (CMOS) platform is very promising for future applications, as those hybrid systems can exploit the benefits of both materials: i.e. the well-developed fabrication platform for Si and the outstanding performance of graphene-based devices [6,7]. As a material basis for realizing such devices on Si, graphene grown by chemical vapor deposition (CVD) on a catalytic metal together with a subsequent transfer process [8] is currently one of the best options, as the direct growth of graphene on Si or SiO2 does not yet provide sufficient material quality [9,10]. However, significant challenges related to the fabrication process limit the exploitation of the ultimate performance potential of graphene-based devices in a CMOS environment. One major issue, especially for graphene devices with sub-micrometer dimensions, is the contact resistance between the graphene and the contact metal [11]. So far, significant efforts have been made to reduce the contact resistance. For instance, the contact metal itself has a significant impact on the contact resistance because of the work-function difference and the bonding strength between the metal and graphene [12-16]. Also, impurities and contamination at the graphene-metal interface affect the contact resistance, and different cleaning and pretreatment procedures have been developed in order to minimize these effects [17-19]. Especially for graphene grown by CVD, surface contamination is a big problem because the transfer process to the target substrate already introduces a significant amount of polymer residuals [20]. An alternative route for realizing low ohmic contacts to CVD-grown graphene avoiding the impact of surface contamination is the formation of edge contacts [21], which has been demonstrated to provide a width specific contact resistance RcW in the range of 100

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to 1900 Ωµm [21,22]. However, these relatively low RcW values have only been realized using noble metals like Au or Pd, which are not compatible with standard CMOS processing. In this paper we report on an efficient procedure for fabricating edge contacts to large area CVD-grown graphene with RcW down to 130 Ωµm using Ni/Al contacts, two metals widely used in CMOS processing. Using Transfer Length Method (TLM) [23] electrical characterization and in addition Kelvin Probe Force Microscopy (KPFM), we conducted a systematic study to extract Rc at the metal-graphene (M-G) interface for top- and edge- contacted devices. While TLM measurements are widely used to extract Rc in graphene devices, a large fitting uncertainty often does not allow a precise extraction of Rc. Additionally, by using TLM the measurement of Rc of an individual metal-graphene contact is not possible. Therefore, we studied the voltage drop of individual two-terminal devices by means of KPFM

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