Machine Learning Based Fast Power Integrity Classifier

In this paper, we proposed a new machine learning based fast power integrity classifier that quickly flags the EM/IR hotspots. We discussed the features to extract to describe the power grid, cell power density, routing impact and controlled collapse chip connection (C4) bumps, etc. The continuous and discontinuous cases are identified and treated using different machine learning models. Nearest neighbors, random forest and neural network models are compared to select the best performance candidates. Experiments are run on open source benchmark, and result is showing promising prediction accuracy.

💡 Research Summary

The paper addresses the growing challenge of power‑integrity verification in modern high‑performance IC design, where increasing power density leads to severe IR‑drop and electromigration (EM) problems. Traditional sign‑off tools provide accurate analysis but require extensive runtime, often forcing designers to iterate through ECO, placement, and floor‑planning stages, which dramatically lengthens the design cycle. To mitigate this, the authors propose a fast, machine‑learning‑based binary classifier that can be applied after placement to flag potential EM/IR hotspots early in the flow.

Methodology Overview
The core idea is to partition the chip into small analysis windows (5 µm × 5 µm) and represent each window with a feature vector (FV) that captures three aspects of the power‑integrity environment:

1. Power Delivery Network (PDN) – for each metal layer i, the width (w_i), pitch (p_i), and offset (o_i) are recorded, providing a concise description of the physical grid geometry.
2. Cell Power Density Map – once placement is fixed, the power consumption of each standard cell is mapped onto a grid of sub‑windows (pd_i,j), preserving the spatial distribution of static power.
3. Signal‑Routing Impact – the total coupling capacitance (c) within the window is summed, reflecting the secondary load imposed by signal routing.

In addition, the distances from the window centre to the nine nearest C4 bumps (X_i, Y_i) are included because C4 bumps act as ideal voltage sources and define the boundary conditions for the PDN. The authors also discuss optional extensions such as process variation and temperature, but these are not central to the experimental evaluation.

Continuous vs. Discontinuous Cases
The authors recognize that the assumption of a continuous PDN breaks down at chip edges and corners, where the grid is truncated. Consequently, they define two categories of windows:

• Continuous windows, where the PDN extends uniformly in all directions.
• Discontinuous windows, which include boundary‑corner and boundary‑only cases.

For discontinuous windows, the feature vector is augmented with the coordinates of the PDN’s bounding box (X_a, Y_a, X_b, Y_b) to explicitly inform the model about the missing grid portions.

Model Selection and Training
Using the scikit‑learn library, three classifiers are evaluated:

• K‑Nearest Neighbors (KNN) – a distance‑based, non‑parametric method.
• Random Forest (RF) – an ensemble of decision trees that captures non‑linear interactions.
• Feed‑forward Neural Network (NN) – a multilayer perceptron capable of learning complex mappings.

The authors train separate models for continuous and discontinuous windows. Empirically, KNN yields the highest accuracy on continuous windows because the smooth voltage/current gradients align well with a simple distance metric. In contrast, for discontinuous windows, both RF and NN outperform KNN; the NN shows a slight edge over RF, likely due to its ability to model the irregular boundary effects more flexibly.

Experimental Setup
The methodology is validated on an open‑source OR1200 FPU/FCMP block. Physical design is performed with Synopsys ICC2, and a reference EM/IR analysis is obtained from ANSYS RedHawk, which provides the ground‑truth labels (hotspot vs. non‑hotspot). To generate a diverse set of violations, the authors bias cell power values, creating 42 560 continuous windows and 900 discontinuous windows. The reference analysis reports 427 IR violations and 58 EM violations in the continuous set, and 411 IR violations and 44 EM violations in the discontinuous set.

Results

• Continuous windows: KNN achieves 91.13 % prediction accuracy (no false‑positive count reported).
• Discontinuous windows: The NN reaches 85.71 % accuracy, with 3 false positives out of 900 windows.

These numbers indicate that the classifier’s hotspot detection closely matches the sign‑off tool’s results while offering a dramatically reduced runtime (the paper emphasizes “fast check” but does not provide explicit timing figures).

Contributions

1. A practical feature engineering scheme that condenses PDN geometry, power density, routing capacitance, and C4 bump locations into a compact vector suitable for machine‑learning classification.
2. A dual‑model strategy that treats continuous and boundary‑affected windows separately, thereby preserving high accuracy across the entire chip.
3. Demonstration on a real design block that the approach can replace or complement traditional sign‑off checks, potentially saving design cycles and enabling earlier corrective actions.

Limitations and Future Work
The study assumes a uniform PDN and focuses on static power; dynamic switching activity, temperature gradients, and detailed process variation are only superficially addressed. Moreover, the feature set does not capture long‑range coupling effects that may become significant in advanced nodes. Future research directions suggested include:

• Extending the methodology to non‑uniform grids and dynamic power profiles.
• Incorporating more sophisticated variation models (e.g., spatially correlated random fields).
• Exploring graph‑based neural networks that can directly ingest the PDN topology rather than a handcrafted vector.
• Integrating the classifier into a full design flow to quantify overall cycle‑time reduction and to evaluate its impact on final sign‑off verification.

In summary, the paper presents a compelling case for leveraging lightweight machine‑learning classifiers to provide early‑stage, rapid power‑integrity assessments. By carefully selecting features that reflect the physical realities of the PDN and by distinguishing between continuous and discontinuous regions, the authors achieve high prediction fidelity with minimal computational overhead, opening a path toward more agile and efficient IC design cycles.