An Online Learning Algorithm for Neuromorphic Hardware Implementation

We propose a sign-based online learning (SOL) algorithm for a neuromorphic hardware framework called Trainable Analogue Block (TAB). The TAB framework utilises the principles of neural population coding, implying that it encodes the input stimulus using a large pool of nonlinear neurons. The SOL algorithm is a simple weight update rule that employs the sign of the hidden layer activation and the sign of the output error, which is the difference between the target output and the predicted output. The SOL algorithm is easily implementable in hardware, and can be used in any artificial neural network framework that learns weights by minimising a convex cost function. We show that the TAB framework can be trained for various regression tasks using the SOL algorithm.

💡 Research Summary

The paper introduces a hardware‑oriented online learning rule called Sign‑Based Online Update Learning (SOUL), designed for the Trainable Analogue Block (TAB) neuromorphic framework and a digital Extreme Learning Machine (ELM) implemented on FPGA. Starting from the previously proposed OPIUM (Online Pseudo‑Inverse Update Method), the authors simplify the matrix‑based update by assuming the autocorrelation matrix of hidden activations is a scaled identity (ε·I). This reduces the normalization factor to a scalar and leads to an update term ϕₙ = hₙᵀ/(ε + hₙᵀhₙ). By further fixing the denominator to a constant N, the update becomes a sign‑sign rule:

 wₙ = wₙ₋₁ + sign(eₙ)·sign(hₙᵀ)/N

where eₙ is the output error and hₙ the hidden‑layer activation vector. The rule requires only the signs of error and activation, which can be realized with a single XOR gate and a binary counter per weight. The weight magnitude is stored in an n‑bit counter, the sign in a separate bit, and the learning step size is controlled by a 3‑bit register (add_no) that determines how many counts are added or subtracted each update. This architecture yields an extremely compact learning block (Digital Learning Block, DLB) that can be instantiated for every connection between hidden and output neurons.

In the analog TAB implementation, inputs are projected to a high‑dimensional hidden space using random weights, biases, and systematic offsets; hidden neurons use a tanh transfer function realized with a few transistors. The DLB updates the output weights in real time, allowing the system to learn functions online. In the digital FPGA implementation, a “broken‑stick” nonlinearity (similar to ReLU) is used, and the same DLB circuitry provides weight updates for a digit‑recognition task on the MNIST dataset.

Experimental validation covers two domains:

1. Regression (Python simulation of TAB) – A single‑input‑single‑output (SISO) network with 100 hidden neurons learns sine, sinc, and a more complex function (sin x + x³ + sin x/x). Results show that RMS error drops sharply once the output weight resolution reaches about 8‑11 bits, after which additional bits give diminishing returns. Increasing the number of hidden neurons reduces the number of epochs needed for a given error threshold, and random shuffling of training samples improves convergence, especially for larger hidden layers (>60 neurons). A minimum of ~26 hidden neurons is required to achieve a 3 % RMS error for the sinc function.

2. Classification (FPGA ELM on MNIST) – The SOUL‑trained digital ELM achieves modest classification accuracy (≈85 % or lower), which is below state‑of‑the‑art CNNs but demonstrates real‑time operation with a hardware footprint limited to XOR gates, counters, and simple logic. The learning rate N is set by the weight‑bit width (2ⁿ), and the add_no register can be decreased during training to trade fast early learning for finer final resolution.

The authors discuss trade‑offs: the sign‑sign update is extremely simple and power‑efficient, but it yields slower convergence and lower asymptotic accuracy compared with gradient‑based methods that use precise magnitude information. They suggest possible improvements such as adaptive step‑size scheduling, multi‑bit increment/decrement schemes, or more sophisticated analog nonlinearities to boost accuracy while retaining hardware simplicity.

Overall, the paper demonstrates that a minimalistic, sign‑based learning rule can be directly mapped onto neuromorphic hardware, enabling online learning with negligible computational overhead. While the approach sacrifices some performance, its ultra‑low resource usage makes it attractive for ultra‑low‑power edge devices, large‑scale analog‑digital neuromorphic arrays, and applications where power and area are more critical than maximal classification accuracy.