Design of a Ternary Edge-Triggered D Flip-Flap-Flop for Multiple-Valued Sequential Logic

📝 Abstract

Development of large computerized systems requires both combinational and sequential circuits. Registers and counters are two important examples of sequential circuits, which are widely used in practical applications like CPUs. The basic element of sequential logic is Flip-Flop, which stores an input value and returns two outputs (Q and Q_bar). This paper presents an innovative ternary D Flip-Flap-Flop, which offers circuit designers to customize their design by eliminating one of the outputs if it is not required. This unique feature of the new design leads to considerable power reduction in comparison with the previously presented structures. The proposed design is simulated and tested by HSPICE and 45 nm CMOS technology.

💡 Analysis

Development of large computerized systems requires both combinational and sequential circuits. Registers and counters are two important examples of sequential circuits, which are widely used in practical applications like CPUs. The basic element of sequential logic is Flip-Flop, which stores an input value and returns two outputs (Q and Q_bar). This paper presents an innovative ternary D Flip-Flap-Flop, which offers circuit designers to customize their design by eliminating one of the outputs if it is not required. This unique feature of the new design leads to considerable power reduction in comparison with the previously presented structures. The proposed design is simulated and tested by HSPICE and 45 nm CMOS technology.

📄 Content

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Design of a Ternary Edge-Triggered D Flip-Flap-Flop for Multiple-Valued Sequential Logic

Reza Faghih Mirzaee 1*, Niloofar Farahani 2

1 Department of Computer Engineering, Shahr-e-Qods Branch, Islamic Azad University, Tehran, Iran
2 ECE Department, K. N. Toosi University of Technology, Tehran, Iran

• E-Mail: r.f.mirzaee@qodsiau.ac.ir

Abstract: Development of large computerized systems requires both combinational and sequential circuits. Registers and counters are two important examples of sequential circuits, which are widely used in practical applications like CPUs. The basic element of sequential logic is Flip-Flop, which stores an input value and returns two outputs (Q and Q ). This paper presents an innovative ternary D Flip-Flap-Flop, which offers circuit designers to customize their design by eliminating one of the outputs if it is not required. This unique feature of the new design leads to considerable power reduction in comparison with the previously presented structures. The proposed design is simulated and tested by HSPICE and 45 nm CMOS technology. Keywords: D Flip-Flop, Multiple-Valued Logic, Sequential Logic, Ternary Flip-Flop, Ternary Flip-Flap-Flop, Ternary Latch

1. Introduction Boolean algebra has indeed played an important role in building computerized systems. The significance of binary numeral system is mainly because of the two-valued nature of electronic components, which are open or closed, connected or disconnected, switched on or off. However, a binary device can merely represent two states. For example, a single-bit memory cell can only hold two logic values of ‘0’ and ‘1’, but not more. Multiple-Valued Logic (MVL) aims to compact more information in a single gate or wire by going beyond dualism, and respond to VLSI and real-world applications more efficiently [1, 2]. Its advantages have been confirmed in many applications such as memories, communications, and digital signal processing [3-5]. The most efficient radix for computing and implementing of switching systems is e (≈2.71828), which makes 3 the best integral value [6]. Theoretically, ternary computations are performed a factor of log2 3 (≈1.585) faster than binary. The unbalanced ternary with the number set of {0, 1, 2}3 is the most common representation, and it is known to be an extension to binary logic [7]. Ternary digits (Trits) are implemented in digital electronics by the voltage levels 0V, ½VDD, and VDD, with the common assumption of having only two supply rails, VDD and GND. Thus, the logic value ‘1’ is the result of a simple voltage division between VDD and GND. The realization of large ternary systems depends on the availability of ternary codes and algorithms as well as design and implementation of electronic circuits. Several ternary logical gates and arithmetic components have previously been designed [8-11]. The design and realization of different ternary memory cells like Static [12, 13] and Dynamic [14] Random Access Memories (SRAM and DRAM), Content-Addressable Memory (CAM) [15], and Flip-Flap-Flop (FFF) [16, 17] have been reported in the literature as well.

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Computer circuits consist of both combinational and sequential components. The availability of sequential circuits is a must for developing any practical system. The most promising applications of MVL are memories and arithmetic circuits [7]. In addition, the most essential element of sequential circuitry is Flip-Flop (FF), which is a single-bit memory cell with two stable states. The other practical sequential circuits such as registers and counters are based on this fundamental building block. In ternary logic, the memory cell must be able to hold three different values. The name Flip-Flap-Flop reflects this fact and represents three states. A single-trit R-S latch has been presented in [16] by cross-coupling two ternary NAND gates. Then, it is converted to a ternary D Flip-Flap-Flop (Fig. 1a). Another ternary D F.F.F. has been introduced in [17] by using cross-coupled ternary inverters (Fig. 1b). Both designs are in accord with the standard sequential design process similar to what it happens in binary logic. They use ternary gates to form a memory cell. High static power consumption is their major drawback, mainly because every single ternary component individually dissipates considerable power. This paper includes static power analysis for the mentioned designs. In this paper, an innovative latch is realized by using binary logical gates. It is efficiently convertible into a ternary latch. Then, the entire memory cell is transformed into a ternary edge-triggered D Flip-Flap-Flop. Binary logical gates do not consume as much power as ternary counterparts do. The unbalanced ternary components divide voltage in order to produce logic ‘1’. It causes considerable power dissipation. The correct functionality is tested by simulating the new design with 45 nm Metal-Oxide-Se

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