Investigation of Dependence between Time-zero and Time-dependent Variability in High-k NMOS Transistors

📝 Abstract

Bias Temperature Instability (BTI) is a major reliability concern in CMOS technology, especially with High dielectric constant (High-\k{appa}/HK) metal gate (MG) transistors. In addition, the time independent process induced variation has also increased because of the aggressive scaling down of devices. As a result, the faster devices at the lower threshold voltage distribution tail experience higher stress, leading to additional skewness in the BTI degradation. Since time dependent dielectric breakdown (TDDB) and stress-induced leakage current (SILC) in NMOS devices are correlated to BTI, it is necessary to investigate the effect of time zero variability on all these effects simultaneously. To that effect, we propose a simulation framework to model and analyze the impact of time-zero variability (in particular, random dopant fluctuations) on different aging effects. For small area devices (~1000 nm2) in 30nm technology, we observe significant effect of Random Dopant Fluctuation (RDF) on BTI induced variability ({\sigma}{\Delta}Vth). In addition, the circuit analysis reveals similar trend on the performance degradation. However, both TDDB and SILC show weak dependence on RDF. We conclude that the effect of RDF on Vth degradation cannot be disregarded in scaled technology and needs to be considered for variation tolerant circuit design.

💡 Analysis

Bias Temperature Instability (BTI) is a major reliability concern in CMOS technology, especially with High dielectric constant (High-\k{appa}/HK) metal gate (MG) transistors. In addition, the time independent process induced variation has also increased because of the aggressive scaling down of devices. As a result, the faster devices at the lower threshold voltage distribution tail experience higher stress, leading to additional skewness in the BTI degradation. Since time dependent dielectric breakdown (TDDB) and stress-induced leakage current (SILC) in NMOS devices are correlated to BTI, it is necessary to investigate the effect of time zero variability on all these effects simultaneously. To that effect, we propose a simulation framework to model and analyze the impact of time-zero variability (in particular, random dopant fluctuations) on different aging effects. For small area devices (~1000 nm2) in 30nm technology, we observe significant effect of Random Dopant Fluctuation (RDF) on BTI induced variability ({\sigma}{\Delta}Vth). In addition, the circuit analysis reveals similar trend on the performance degradation. However, both TDDB and SILC show weak dependence on RDF. We conclude that the effect of RDF on Vth degradation cannot be disregarded in scaled technology and needs to be considered for variation tolerant circuit design.

📄 Content

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Abstract— Bias Temperature Instability (BTI) is a major reliability concern in CMOS technology, especially with High dielectric constant (High-κ/HK) metal gate (MG) transistors. In addition, the time independent process induced variation has also increased because of the aggressive scaling down of devices. As a result, the faster devices at the lower threshold voltage distribution tail experience higher stress, leading to additional skewness in the BTI degradation. Since time dependent dielectric breakdown (TDDB) and stress-induced leakage current (SILC) in NMOS devices are correlated to BTI, it is necessary to investigate the effect of time zero variability on all these effects simultaneously. To that effect, we propose a simulation framework to model and analyze the impact of time-zero variability (in particular, random dopant fluctuations) on different aging effects. For small area devices (~1000 nm2) in 30nm technology, we observe significant effect of Random Dopant Fluctuation (RDF) on BTI induced variability (σΔVth). In addition, the circuit analysis reveals similar trend on the performance degradation. However, both TDDB and SILC show weak dependence on RDF. We conclude that the effect of RDF on Vth degradation cannot be disregarded in scaled technology and needs to be considered for variation tolerant circuit design.

Index Terms— Bias Temperature Instability, Variability, Reliability, High- κ dielectrics, TDDB, SILC.

I. INTRODUCTION N order to aggressively downscale devices and suppress the standby leakage current, HfO2 based HKMG transistors were adopted recently by the IC industry [1]. Their advantages over conventional silicon oxynitride (SiON) devices have already been demonstrated to a great extent in different literature [1-3]. However, this changeover in technology roadmap brings about new failure mechanisms (such as Positive Bias Temperature Instability (PBTI), Stress Induced Leakage Currents (SILC), etc.) that enhanced the complexity in reliability quantification [4-6]. Due to the presence of d- shell electrons and relatively higher coordination number, high-κ oxides are vulnerable to both native and time dependent stress induced defect formation [7-8]. Since HfO2 bulk traps cannot be charged under negative stress voltage,

 This work is funded in part by the National Science Foundation. 

The authors are with the School of Electrical and Computer Engineering at Purdue University, West Lafayette, IN 47907 (email: khaled@purdue.edu, kaushik@purdue.edu)

these defects only affect the threshold voltage and leakage
current of NMOSFETs [4]. Along with the time dependent BTI induced variation, the on -die/die-to-die and parameter variations play a critical role in reliability assessment at both device and circuit level [9-10]. In sub-45nm technology, the native oxide thickness has gone down to 2 or 3 atomic layers. Consequently, it is important to understand the nature of σΔVth with the change in device dimensions. In addition, the dependence between time-zero and time dependent variability needs to be properly addressed. The devices at the lower process induced distribution tail performs faster (Fig. 1) due to their low turn-on voltage compared to the nominal threshold voltage, Vth(0). The variation can be up to few sigma values (σVth(0)) of the time-zero variation. This increases the stress voltage across the high-κ and interfacial layer (IL), causing faster trap generation in the corresponding oxide layers. As an example, in order to comprehend the nature of RDF and temporal BTI evolution and their dependence, it is important to capture the effect of each dopant in the channel region and defect in the bulk oxide layers simultaneously and determine the corresponding effect on Vth degradation. Therefore, a complete modeling framework for RDF as well as BTI variation considering the fluctuation in number and position of independent dopants and their impact on oxide defects/traps is necessary for circuit analysis.

Fig. 1: Time-zero variation (δVth(0)) with respect to the nominal threshold voltage, Vth(0) can be up to few σVth(0). This can cause a non-uniform stress voltage distribution across the oxide layers.

Investigation of Dependence between Time-zero and Time-dependent Variability in High-κ NMOS Transistors
Mohammad Khaled Hassan, Student Member, IEEE and Kaushik Roy, Fellow, IEEE

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Fig. 2: Our simulation framework.

The rest of the paper is organized as follows. In section II, we explained our modeling and simulation framework. In this section, we have briefly introduced the PBTI model proposed in [11] and our extended model in order to analyze time dependent oxide wear outs. Sec

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