Complete DFM Model for High-Performance Computing SoCs with Guard Ring and Dummy Fill Effect

📝 Abstract

For nanotechnology, the semiconductor device is scaled down dramatically with additional strain engineering for device enhancement, the overall device characteristic is no longer dominated by the device size but also circuit layout. The higher order layout effects, such as well proximity effect (WPE), oxide spacing effect (OSE) and poly spacing effect (PSE), play an important role for the device performance, it is critical to understand Design for Manufacturability (DFM) impacts with various layout topology toward the overall circuit performance. Currently, the layout effects (WPE, OSE and PSE) are validated through digital standard cell and analog differential pair test structure. However, two analog layout structures: the guard ring and dummy fill impact are not well studied yet, then, this paper describes the current mirror test circuit to examine the guard ring and dummy fills DFM impacts using TSMC 28nm HPM process.

💡 Analysis

For nanotechnology, the semiconductor device is scaled down dramatically with additional strain engineering for device enhancement, the overall device characteristic is no longer dominated by the device size but also circuit layout. The higher order layout effects, such as well proximity effect (WPE), oxide spacing effect (OSE) and poly spacing effect (PSE), play an important role for the device performance, it is critical to understand Design for Manufacturability (DFM) impacts with various layout topology toward the overall circuit performance. Currently, the layout effects (WPE, OSE and PSE) are validated through digital standard cell and analog differential pair test structure. However, two analog layout structures: the guard ring and dummy fill impact are not well studied yet, then, this paper describes the current mirror test circuit to examine the guard ring and dummy fills DFM impacts using TSMC 28nm HPM process.

📄 Content

 Abstract— For nanotechnology, the semiconductor device is scaled down dramatically with additional strain engineering for device enhancement, the overall device characteristic is no longer dominated by the device size but also circuit layout. The higher order layout effects, such as well proximity effect (WPE), oxide spacing effect (OSE) and poly spacing effect (PSE), play an important role for the device performance, it is critical to understand Design for Manufacturability (DFM) impacts with various layout topology toward the overall circuit performance. Currently, the layout effects (WPE, OSE and PSE) are validated through digital standard cell and analog differential pair test structure. However, two analog layout structures: the guard ring and dummy fill impact are not well studied yet, then, this paper describes the current mirror test circuit to examine the guard ring and dummy fills DFM impacts using TSMC 28nm HPM process.

Index Terms — DFM, SoC, WPE, OSE, PSE, high-performance computing, guard ring, dummy fill

I. INTRODUCTION With advance of nanotechnology, the semiconductor device is scaled down rapidly with additional strain engineering for device enhancement, the overall device characteristic is no longer dominated by the device size but also layout effects (WPE, OSE and PSE) [1]. It is critical to understand Design for Manufacturability (DFM) impacts with various layout topology toward the overall circuit performance. Currently, the digital standard cell and analog differential pair layout test structure are implemented to validate the layout effects. However, two important analog circuit layout topology: guard ring and dummy fill impact are not well studied yet. Therefore, this paper describes a current mirror test circuit to examine the guard ring and dummy fills DFM impacts using TSMC 28nm HPM process. For analog design, the circuit performance is highly dependent on the device matching, then, the centroid topology is often chosen to minimize the layout environmental variation. The transistors are arranged symmetrically in centroid style where all the devices suffer from the same physical and electrical impacts from all directions. The centroid topology focuses the active devices layout impacts only, the guard ring protection and dummy fill layout structures are not fully taken into consideration yet. At a result, the modified current mirror

configurations are implemented to explore various guard ring and dummy fill DFM impacts.

II. MODIFIED TEST STRUCTURE In Figure 1, it is shown the conventional current mirror [2] centroid layout topology, the multi-finger devices: MA and MB are placed alternatively and symmetrically, the individual transistor experience same layout impacts, they suffer same physical and electrical impacts from all direction [3]. This layout topology is originally developed to minimize the angular implant doping variation, it is further enforced to reduce layout effects (WPE, OSE and PSE) impacts since 45nm process [4][5]. This paper focuses on the fine centroid layout style rather than the coarse one where a group of transistors are arranged symmetrically to minimize high interconnect RC parasitic impacts. In order to isolate the current mirror from other impacts, the active devices are protected by guard ring and diffusion (OD)/poly (PO) dummy. The guard ring is typically used to protect the active devices from latch-up and noise interference where P+ guard ring with VSS connection protects NMOS active devices, PMOS active devices surrounds with N+ guard ring connected to VDD as shown in Figure 2. There are two kinds of guard ring: single and double guard ring where the single guard ring employs either P+ or N+ guard ring only, the double guard ring mixes with both P+ and N+ guard ring. Currently, the simulation model only considers the active device layout effect impacts, it ignores the physical and electrical impacts introduced by guard ring. Only diffusion spacing between active devices and guard ring are considered in simulation using OSE model. The guard ring diffusion width and P+/N+ implant type both contribute to the device mobility changes. Therefore, we propose to modify the original OSE Chun-Chen Liu, Oscar Lau, Jason Y. Du University of California, Los Angeles yuandu@ucla.edu
Complete DFM Model for High-Performance Computing SoCs with Guard Ring and Dummy Fill Effect

Figure 1. NMOS Current Mirror Fine Centroid Topology model [6] by introducing effective STI width (STIWeff) parameter. As a first-order model, we set a threshold of OD width of single guard ring (ODWth) when guard ring effect comes into play. The value of ODWth can be found by experiment. If ODW is smaller than ODWth, then the STIeff is defined as

𝑆𝑇𝐼𝑊𝑒𝑓𝑓= 𝑆𝑇𝐼𝑊× (1 + 𝐾 𝑂𝐷𝑊𝑡ℎ 𝑂𝐷𝑊) (1) where K is curve fitting parameter.

Dummy fill is typically related with three different t

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