Radio Frequency Modulated Signaling Interconnect for Memory-to-Processor and Processor-to-Processor Interfaces: An Overview

📝 Abstract

With the evolution of heterogeneous computing system, such as network-on-chip, high-performance distributed computing, accelerator-rich architectures and cluster computing, high-speed, energy-efficient and low-latency interfaces among memory-to-processor and processor-to-processor become the key technology to enable those technologies. Simultaneously, the scaling of CMOS makes the switching speed of the transistor up to sub-THz. Radio-frequency or even millimeter-wave modulated signaling interconnect has unique features in ultra-low power operation, dynamic allocation of bandwidth and low latency, compared with convention baseband signaling interconnect. In this work, we overview the different generations of radio-frequency interconnect (RF-I) technology, compare them with conventional baseband signaling interconnect technologies. The limitations and potentials are also discussed in the end.

💡 Analysis

With the evolution of heterogeneous computing system, such as network-on-chip, high-performance distributed computing, accelerator-rich architectures and cluster computing, high-speed, energy-efficient and low-latency interfaces among memory-to-processor and processor-to-processor become the key technology to enable those technologies. Simultaneously, the scaling of CMOS makes the switching speed of the transistor up to sub-THz. Radio-frequency or even millimeter-wave modulated signaling interconnect has unique features in ultra-low power operation, dynamic allocation of bandwidth and low latency, compared with convention baseband signaling interconnect. In this work, we overview the different generations of radio-frequency interconnect (RF-I) technology, compare them with conventional baseband signaling interconnect technologies. The limitations and potentials are also discussed in the end.

📄 Content

 Abstract— With the evolution of heterogeneous computing system, such as network-on-chip, high-performance distributed computing, accelerator-rich architectures and cluster computing, high-speed, energy-efficient and low-latency interfaces among memory-to-processor and processor-to-processor become the key technology to enable those technologies. Simultaneously, the scaling of CMOS makes the switching speed of the transistor up to sub-THz. Radio-frequency or even millimeter-wave modulated signaling interconnect has unique features in ultra-low power operation, dynamic allocation of bandwidth and low latency, compared with convention baseband signaling interconnect. In this work, we overview the different generations of radio-frequency interconnect (RF-I) technology, compare them with conventional baseband signaling interconnect technologies. The limitations and potentials are also discussed in the end.

Index Terms — interconnect, memory-to-processor, processor-to-processor, radio frequency modulated signaling, energy efficiency, radio-frequency interconnect (RF-I)

I. INTRODUCTION o meeting the even-increasing computation-intensive applications and the demands of low-power, low-cost and high-performance system, the number of heterogeneous computing systems in a single chip has enormously increased, such as network-on-chip (NoC), high-performance distributed computing (HPDC), accelerator-rich architectures (ARA) and cluster computing (CC) [1]. The key and common requirement of those systems are a high-speed, energy-efficient and low-latency interconnect technology, which supports communication among memory to the processor, processor to processor, accelerator to memory, accelerator to accelerator, and accelerator to processor. Microsoft’s Project Catapult is a great example in hyper-scale cloud-based acceleration by utilizing conventional baseband high-speed interconnects on Altera’s Stratix V D5 FPGA [2].
At the same time with the key benefits of the ultra-scaling CMOS technology, the switching speed of transistor increases a lot over each technology node. Based on ITRS reports [3], fT and fmax, will exceed 800 GHz and 1 THz, respectively in 10nm CMOS technology. With the advance of CMOS radio-frequency and millimeter-wave circuits, higher and higher bandwidth will be available shortly. Recently, many published works demonstrated millimeter-wave band more

than 60 GHz [4-9] and even up to THz range [10-14]. With more frequency band resources, CMOS-based circuits are driving all kinds of radio-frequency related applications. For instance, the CMOS RF circuits are used for wireless and wireline communication [15-21], human-machine interfaces [22-24], navigation [25], etc.
Power consumption and heat dissipation are very critical issues of modern high-performance computing platform [2]. For example, Fig. 1 shows that the serial interface power consumption is almost comparable with computing core’s power. Another example published by Intel, saying the serial interface power is going to exceed 50% of total CPU power with higher and higher IO data rate in the very near future. In this paper, the conventional baseband signaling interconnects, and equalization techniques will be reviewed in Section II and III. In Section IV and V, we will introduce radio-frequency signaling concept and summarizes the radio-frequency interconnect (RF-I) technology development generation by generation. Section VI will draw the conclusion.

II. CONVENTIONAL BASEBAND SIGNALING INTERCONNECT
The data rate of peripheral serial input/output (I/O) for PC and mobile computing platforms continue to scale to meet high-bandwidth applications including high-resolution displays, camera sensors and large-capacity external storage [26]. In Fig. 2 (a) the blue curve is technology scaling, and the red curve is the number of functions per chip, increasing dramatically with technology scaling.
Radio Frequency Modulated Signaling Interconnect for Memory-to-Processor and Processor-to-Processor Interfaces: An Overview Jason Y. Du, Student Member, IEEE T [Oracle T3 processor] [Intel JSSC 2013]
Fig. 1 Trend of power consumption of interconnect More interestingly, Fig. 2 (b) shows that the CPU clock rate does not change much over 15 years, mainly because power and heat dissipation becomes a severe problem. Moreover, similarly, the IO pads number per chip also remains relatively constant but for a different reason, mainly because of packaging cost. Nowadays, the packaging plus testing have already taken more portion than fabrication in the semiconductor industry, especially for high-speed high-pin-count chips. It is very obvious that there is a large gap between IO data rate and internal data rate, 15 ~ 20 times difference.
Interconnect design evolved a lot over these years as Fig. 2 shows. Starting from 1980’s, when the data

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