Enabling Bio-Plausible Multi-level STDP using CMOS Neurons with Dendrites and Bistable RRAMs

📝 Abstract

Large-scale integration of emerging nanoscale non-volatile memory devices, e.g. resistive random-access memory (RRAM), can enable a new generation of neuromorphic computers that can solve a wide range of machine learning problems. Such hybrid CMOS-RRAM neuromorphic architectures will result in several orders of magnitude reduction in energy consumption at a very small form factor, and herald autonomous learning machines capable of self-adapting to their environment. However, the progress in this area has been impeded from the realization that the actual memory devices fall well short of their expected behavior. In this work, we discuss the challenges associated with these memory devices and their use in neuromorphic computing circuits, and propose pathways to overcome these limitations by introducing ‘dendritic learning’.

💡 Analysis

Large-scale integration of emerging nanoscale non-volatile memory devices, e.g. resistive random-access memory (RRAM), can enable a new generation of neuromorphic computers that can solve a wide range of machine learning problems. Such hybrid CMOS-RRAM neuromorphic architectures will result in several orders of magnitude reduction in energy consumption at a very small form factor, and herald autonomous learning machines capable of self-adapting to their environment. However, the progress in this area has been impeded from the realization that the actual memory devices fall well short of their expected behavior. In this work, we discuss the challenges associated with these memory devices and their use in neuromorphic computing circuits, and propose pathways to overcome these limitations by introducing ‘dendritic learning’.

📄 Content

Enabling Bio-Plausible Multi-level STDP using CMOS Neurons with Dendrites and Bistable RRAMs
Xinyu Wu Boise, ID, USA tomas.wu@gmail.com Vishal Saxena Department of Electrical and Computer Engineering University of Idaho Moscow, ID, USA vsaxena@uidaho.edu

Abstract— Large-scale integration of emerging nanoscale non-volatile memory devices, e.g. resistive random-access memory (RRAM), can enable a new generation of neuromorphic computers that can solve a wide range of machine learning problems. Such hybrid CMOS-RRAM neuromorphic architectures will result in several orders of magnitude reduction in energy consumption at a very small form factor, and herald autonomous learning machines capable of self-adapting to their environment. However, the progress in this area has been impeded from the realization that the actual memory devices fall well short of their expected behavior. In this work, we discuss the challenges associated with these memory devices and their use in neuromorphic computing circuits, and propose pathways to overcome these limitations by introducing ‘dendritic learning’. Keywords—Neuromorphic; Resistive Memory; Stochastic Computing; Spike-Timing Dependent Plasticity I. INTRODUCTION Human brain is capable of processing unstructured information sensed from the environment, and performing real- time pattern discovering and recognition tasks in a remarkably fast, accurate, robust, and energy-efficient manner. Thanks to a half century of advances in semiconductor technology, modern computers can perform such tasks but still require orders of magnitude higher energy, as well as specialized programming. Massive parallelism, event-driven spike-based communication and in-situ synaptic plasticity are believed to be responsible for brain’s effective and energy-efficient information processing. Recently, brain-inspired neuromorphic hardware have demonstrated impressive ultra-low power performance in implementing convolutional neural networks [1]. However, it is not amenable to accommodate a huge number of synapses and cannot adjust the synaptic weights while in operation. In the past decade, the discovery of spike-timing-dependent- plasticity (STDP) and emerging of nanoscale resistive random- access memory (RRAM) devices has opened new avenues towards the realization of brain-inspired computing. Many RRAMs have demonstrated small feature size (4F2), ultra- energy-efficiency (pJ/switch), CMOS compatible and 3D integration capability, and exhibit bio-plausible STDP characteristics [2], [3]. Studies also suggested STDP can be used to train spiking neural networks (SNNs) with RRAM synapses in-situ without trading-off their parallelism [4], [5].
Consequently, it is natural to envision hybrid CMOS-RRAM very-large-scale integrated (VLSI) circuits to achieve dense integration of CMOS neurons and RRAM synapses to build neural-inspired computing chips by leveraging the nanometer scale silicon processing technology. Recently, mixed-signal chips with spiking neurons that can interface with RRAM devices, and learning algorithms and circuits built using these neural motifs have been demonstrated by the authors [6]–[8]. A densely-integrated CMOS-RRAM spiking neural network, with non-volatile analog-like weights, is ideal for such realization [4], [7]. However, neuromorphic circuit community is facing challenges in practical realization of these implementations, where a major roadblock is the bistable and probabilistic switching behavior of RRAM [9]–[12]. A majority of small-size RRAMs exhibits abrupt switching nature, which in consequence limits stable synaptic resolution to 1-bit (or binary, bistable); furthermore, their switching probability and switching time are typically depends on the voltage applied to the device, as well as the duration of the voltage pulse. Fig. 1 illustrated the abrupt resistance decrease (SET) and the corresponding switching dependence on the voltage in a HfOx RRAM device [13]. To circumvent these issues, compound memristive synapse with multiple bistable devices in parallel was recently proposed to emulate analog weights [12]–[14]. Moreover, a standard pattern classification application has shown that least 4-bit of synaptic resolution is needed to achieve reasonable recognition performance [15]. However, simply placing multiple bistable RRAM in parallel doesn’t result in the expected exponentially shaped learning

Fig.1. Binary stochastic switching and the STDP in RRAM. (A) Abrupt SET transition starting from the off-state by repetitive SET pulses. (B) Measured statistical distribution of pulse amplitude required for triggering the SET switching from the off-state (adapted from [13]).
Pulse Number Resistance (Ω) SET Pulse Threshold (V) Probability Density (%) A B 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 2 .6 0 5 10 15 2

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