Assessing Random Dynamical Network Architectures for Nanoelectronics

📝 Abstract

Independent of the technology, it is generally expected that future nanoscale devices will be built from vast numbers of densely arranged devices that exhibit high failure rates. Other than that, there is little consensus on what type of technology and computing architecture holds most promises to go far beyond today’s top-down engineered silicon devices. Cellular automata (CA) have been proposed in the past as a possible class of architectures to the von Neumann computing architecture, which is not generally well suited for future parallel and fine-grained nanoscale electronics. While the top-down engineered semi-conducting technology favors regular and locally interconnected structures, future bottom-up self-assembled devices tend to have irregular structures because of the current lack precise control over these processes. In this paper, we will assess random dynamical networks, namely Random Boolean Networks (RBNs) and Random Threshold Networks (RTNs), as alternative computing architectures and models for future information processing devices. We will illustrate that–from a theoretical perspective–they offer superior properties over classical CA-based architectures, such as inherent robustness as the system scales up, more efficient information processing capabilities, and manufacturing benefits for bottom-up designed devices, which motivates this investigation. We will present recent results on the dynamic behavior and robustness of such random dynamical networks while also including manufacturing issues in the assessment.

💡 Analysis

Independent of the technology, it is generally expected that future nanoscale devices will be built from vast numbers of densely arranged devices that exhibit high failure rates. Other than that, there is little consensus on what type of technology and computing architecture holds most promises to go far beyond today’s top-down engineered silicon devices. Cellular automata (CA) have been proposed in the past as a possible class of architectures to the von Neumann computing architecture, which is not generally well suited for future parallel and fine-grained nanoscale electronics. While the top-down engineered semi-conducting technology favors regular and locally interconnected structures, future bottom-up self-assembled devices tend to have irregular structures because of the current lack precise control over these processes. In this paper, we will assess random dynamical networks, namely Random Boolean Networks (RBNs) and Random Threshold Networks (RTNs), as alternative computing architectures and models for future information processing devices. We will illustrate that–from a theoretical perspective–they offer superior properties over classical CA-based architectures, such as inherent robustness as the system scales up, more efficient information processing capabilities, and manufacturing benefits for bottom-up designed devices, which motivates this investigation. We will present recent results on the dynamic behavior and robustness of such random dynamical networks while also including manufacturing issues in the assessment.

📄 Content

Assessing Random Dynamical Network Architectures for Nanoelectronics Christof Teuscher1, Natali Gulbahce2, Thimo Rohlf3 1Computer, Computational & Statistical Sciences Division, Los Alamos National Laboratory, USA, christof@teuscher.ch 2Center for Complex Networks Research, Northeastern University, USA, natali.gulbahce@gmail.com 3Max Planck Institute for Mathematics in the Sciences, Leipzig, Germany, rohlf@santafe.edu Abstract— Independent of the technology, it is generally ex- pected that future nanoscale devices will be built from vast numbers of densely arranged devices that exhibit high failure rates. Other than that, there is little consensus on what type of technology and computing architecture holds most promises to go far beyond today’s top-down engineered silicon devices. Cellular automata (CA) have been proposed in the past as a possible class of architectures to the von Neumann computing architecture, which is not generally well suited for future mas- sively parallel and fine-grained nanoscale electronics. While the top-down engineered semi-conducting technology favors regular and locally interconnected structures, future bottom-up self- assembled devices tend to have irregular structures because of the current lack of precise control over these processes. In this paper, we will assess random dynamical networks, namely Random Boolean Networks (RBNs) and Random Threshold Networks (RTNs), as alternative computing architectures and models for future information processing devices. We will illustrate that— from a theoretical perspective—they offer superior properties over classical CA-based architectures, such as inherent robustness as the system scales up, more efficient information processing capabilities, and manufacturing benefits for bottom-up designed devices, which motivates this investigation. We will present recent results on the dynamic behavior and robustness of such random dynamical networks while also including manufacturing issues in the assessment. I. INTRODUCTION AND MOTIVATION The advent of multicore architectures and the slowdown of the processor’s operating frequency increase are signs that CMOS miniaturization is increasingly hitting fundamental physical limits. A key question is how computing architectures will evolve as we reach these fundamental limits. A likely possibility within the realm of CMOS technology is that the integration density will cease to increase at some point, instead only the number of components, i.e, the transistors, will further increase, which will necessarily lead to chips with a higher area. This trend can already be observed with multi-core ar- chitectures. That in itself has implications on the interconnect architecture, the power consumption and dissipation, and the reliability. Another possibility is to go beyond silicon-based technology and to change the computing and manufacturing paradigms, by using for example bottom-up self-assembled devices. Self-assembling nanowires [12] or carbon nanotube electronics [2] are promising candidates, although none of them has resulted in electronics that is able to compete with traditional CMOS so far. What seems clear is that the current way with build computers and the way we algorithmically solve problems with them may need to be fundamentally revisited, which this paper is all about. While the top-down engineered CMOS technology favors regular and locally interconnected structures, future bottom- up self-assembled devices tend to have irregular structures because of the current lack of precise control over these processes. We therefore hypothesize that future and emerging computing architectures will be much more driven by manu- facturing constraints and particularities than for CMOS, which allowed engineers to implement a logic-based computing ar- chitecture with extreme precision and reliability, at least in the past. Independent of the forthcoming device and fabrication technologies, it is generally expected that future nanoscale devices will be built from (1) vast numbers of densely arranged devices that (2) exhibit high failure rates. We take this working hypothesis for granted in this paper and address it from a perspective that focuses on the interconnect topology. This is justified by the fact that the importance of interconnects on electronic chips has outrun the importance of transistors as a dominant factor of performance [9], [15], [25]. The reasons are twofold: (1) the transistor switching speed for traditional silicon is much faster than the average wire delays and (2) the required chip area for interconnects has dramatically increased. In [45], Zhirnov et al. explored integrated digital Cellu- lar Automata (CA) architectures—which are highly regular structures with local interconnects (see Section III)—as an alternative paradigms to the von Neumann computer architec- ture for future and emerging information processing devices. Here, we are interested to explore and assess a more general class of d

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