An overview about Networks-on-Chip with multicast suppor

📝 Abstract

Modern System-on-Chip (SoC) platforms typically consist of multiple processors and a communication interconnect between them. Network-on-Chip (NoC) arises as a solution to interconnect these systems, which provides a scalable, reusable, and an efficient interconnect. For these SoC platforms, multicast communication is significantly used for parallel applications. Cache coherency in distributed sharedmemory,clock synchronization, replication, or barrier synchronization are examples of these requests. This paper presents an overview of research on NoC with support for multicast communication and delineates the major issues addressed so far by the scientific community in this investigation area.

💡 Analysis

Modern System-on-Chip (SoC) platforms typically consist of multiple processors and a communication interconnect between them. Network-on-Chip (NoC) arises as a solution to interconnect these systems, which provides a scalable, reusable, and an efficient interconnect. For these SoC platforms, multicast communication is significantly used for parallel applications. Cache coherency in distributed sharedmemory,clock synchronization, replication, or barrier synchronization are examples of these requests. This paper presents an overview of research on NoC with support for multicast communication and delineates the major issues addressed so far by the scientific community in this investigation area.

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An overview about Networks-on-Chip with multicast support Marcelo Daniel Berejuck Software and Hardware Integration Laboratory Federal University of Santa Catarina Rua Pedro João Pereira, 150, 88.905-120 - Araranguá SC - Brazil marcelo.berejuck@ufsc.br Abstract—Modern System-on-Chip (SoC) platforms typically consist of multiple processors and a communication interconnect between them. Network-on-Chip (NoC) arises as a solution to interconnect these systems, which provides a scalable, reusable, and an efficient interconnect. For these SoC platforms, multicast communication is significantly used for parallel applications. Cache coherency in distributed shared- memory, clock synchronization, replication, or barrier synchronization are examples of these requests. This paper presents an overview of research on NoC with support for multicast communication and delineates the major issues addressed so far by the scientific community in this investigation area. Network-on-Chip; Multicast; System-on-Chip. I. INTRODUCTION The silicon industry has used Systems-on-Chip with multiple heterogeneous processing units as means to deliver the performance required by modern applications. However, the integration of an increasing number of specialized processing units poses a challenge on the interconnection mechanisms in such systems. As a solution, the silicon industry has been using Networks-on-Chip to interconnect components in this kind of SoC [1], [2]. The Communication in NoC can be either unicast or multicast [3]. In unicast communication, a message is sent from a processor connected to the network to a single destination processor. In multicast communication, a message is sent from one processor to an arbitrary set of destination processors in the network. Several SoCs with multiple processors have applications that employ multicast communication, for example, barrier synchronization, cache coherency in distributed shared- memory architectures, or clock synchronization. Despite the multicast communication can be implemented by multiple unicast communications, it is not a suitable strategy because it degrades the performance and increases the congestion in the network [4]. This paper presents an overview of research on NoC with support for multicast communication and delineates the major issues addressed by the scientific community in this research area over the last decade. It starts with an overview about Network-on-Chip and Multicast in Section II. Section III introduces an overview of research that has done on multicast communication for Networks-on-Chip, and Section IV close this paper with our conclusion. II. BACKGROUND A. Network-on-Chip basics A NoC consists of a structure of routers and links implementing a packet-switched communication fabric, and Figure 1 depicts an example of 2x2 NoC with four nodes. A node is defined here as a set composed of a router, a network adapter and one core as highlighted in Figure 2(c). Network adapter (NA) acts as a bridge from the packet-switched interconnect to a core connected to the network. For MPSoC based on NoC, a core is typically a processor with some amount of local memory. In Figure 1, IM and DM represent instruction and data memories, which can be a cache or a scratch-pad memory. The core can also be a slave device, such as a controller for a larger amount of external memory shared by several cores, or an Input / Output controller. Figure 1. Example of a NoC with four nodes. Processing cores attached to the NoC communicate by sending and receiving messages through the network. A header, a payload, and a trailer compose messages. The header flit has routing information that guides the packet through the network up to the destination node. The payload to routers along the path that it is the last flit of the packet, and other packets can use the resources (i.e. router and links). ROUTER NA CORE ROUTER ROUTER ROUTER Bidirectional links NA CORE NA CORE NA CORE PROCESSOR IM DM A Network-on-Chip can be described by its topology and the strategies employed for routing, switching, flow control, arbitration and buffering. A network topology is the arrangement of nodes and channels into a graph, as depicted in Figure 2. A Network may have a regular topology, as shown in Figure 2(a), (b), and (c), or irregular topology illustrated in figure 2(d). Router, highlighted as a white square on the top of Figure 2(c), implements the routing, switching, flow control, arbitration, and buffering functionalities. Routing determines how a message chooses a path in the network. Switching is the mechanism that removes data from an input channel and places it on an output channel. Flow control deals with the allocation of channels and buffers to a message as it traverses this path. Arbitration is responsible for scheduling the use of channels and buffers by the messages. Fin

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