A Proposal for Energy-Efficient Cellular Neural Network based on Spintronic Devices

📝 Abstract

Due to the massive parallel computing capability and outstanding image and signal processing performance, cellular neural network (CNN) is one promising type of non-Boolean computing system that can outperform the traditional digital logic computation and mitigate the physical scaling limit of the conventional CMOS technology. The CNN was originally implemented by VLSI analog technologies with operational amplifiers and operational transconductance amplifiers as neurons and synapses, respectively, which are power and area consuming. In this paper, we propose a hybrid structure to implement the CNN with magnetic components and CMOS peripherals with a complete driving and sensing circuitry. In addition, we propose a digitally programmable magnetic synapse that can achieve both positive and negative values of the templates. After rigorous performance analyses and comparisons, optimal energy is achieved based on various design parameters, including the driving voltage and the CMOS driving size. At a comparable footprint area and operation speed, a spintronic CNN is projected to achieve more than one order of magnitude energy reduction per operation compared to its CMOS counterpart.

💡 Analysis

Due to the massive parallel computing capability and outstanding image and signal processing performance, cellular neural network (CNN) is one promising type of non-Boolean computing system that can outperform the traditional digital logic computation and mitigate the physical scaling limit of the conventional CMOS technology. The CNN was originally implemented by VLSI analog technologies with operational amplifiers and operational transconductance amplifiers as neurons and synapses, respectively, which are power and area consuming. In this paper, we propose a hybrid structure to implement the CNN with magnetic components and CMOS peripherals with a complete driving and sensing circuitry. In addition, we propose a digitally programmable magnetic synapse that can achieve both positive and negative values of the templates. After rigorous performance analyses and comparisons, optimal energy is achieved based on various design parameters, including the driving voltage and the CMOS driving size. At a comparable footprint area and operation speed, a spintronic CNN is projected to achieve more than one order of magnitude energy reduction per operation compared to its CMOS counterpart.

📄 Content

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Abstract Due to the massive parallel computing capability and outstanding image and signal processing performance, cellular neural network (CNN) is one promising type of non-Boolean computing system that can outperform the traditional digital logic computation and mitigate the physical scaling limit of the conventional CMOS technology. The CNN was originally implemented by VLSI analog technologies with operational amplifiers and operational transconductance amplifiers as neurons and synapses, respectively, which are power and area consuming. In this paper, we propose a hybrid structure to implement the CNN with magnetic components and CMOS peripherals with a complete driving and sensing circuitry. In addition, we propose a digitally programmable magnetic synapse that can achieve both positive and negative values of the templates. After rigorous performance analyses and comparisons, optimal energy is achieved based on various design parameters, including the driving voltage and the CMOS driving size. At a comparable footprint area and operation speed, a spintronic CNN is projected to achieve more than one order of magnitude energy reduction per operation compared to its CMOS counterpart.

1. Introduction CMOS scaling has lasted for half a century and almost approaches its fundamental and physical limits [1]. Many novel device technologies have been proposed in the past decade to replace or augment the conventional CMOS technology [2]. To further improve the computing energy efficiency, spintronic devices are developed using electron spin as a state variable to perform logic computation [3-5]. However, despite the large research efforts in the Boolean logic domain, few device concepts have better or comparable performance or energy efficiency than the conventional CMOS technology [2]. Some non-Boolean computing architectures, such as the cellular neural network (CNN) [6], are potential candidates to provide higher energy efficiencies due to their massive parallel processing capability. The CNN also has the advantage of its compatibility with integrated circuits and has a wide range of applications in image and signal processing, such as the pattern recognition and motion tracking [7-9]. A CNN contains an array of computing cells that are connected only with nearby cells. Since interconnects are major limitations in modern VLSI systems, CNN systems can take the advantage of the local communication and encounter small constraints imposed by interconnects. The CNN can be considered as a brain-inspired computing architecture that is based on neurons to integrate the incoming currents. The accumulated and activated output signal drives nearby neurons through weighted synapses. The underlying mathematics of a CNN was proposed by Chua [6] and the dynamic state equation of each CNN cell circuit is written as 𝐶𝑑𝑥𝑖𝑗 𝑑𝑡= −1 𝑅𝑥𝑖𝑗+ ∑𝐴𝑖𝑗,𝑘𝑙𝑦𝑘𝑙 𝑘𝑙∈𝑆𝑖𝑗

• ∑𝐵𝑖𝑗,𝑘𝑙𝑢𝑘𝑙 𝑘𝑙∈𝑆𝑖𝑗
• 𝐼𝑖𝑗, 𝑦𝑖𝑗= 𝑓(𝑥𝑖𝑗) (1)
  where 𝑥𝑖𝑗 is the state voltage of the cell, 𝑅 and 𝐶 are linear resistance and capacitance of each cell, 𝑦𝑘𝑙 and 𝑢𝑘𝑙 are the outputs and inputs of neighboring cells, respectively, 𝑓(𝑥) is the sigmoid function that describes the A Proposal for Energy-Efficient Cellular Neural Network based on Spintronic Devices Chenyun Pan and Azad Naeemi School of Electrical and Computer Engineering,
  Georgia Institute of Technology, Atlanta GA 30332 2

characteristic between the output voltage and cell state voltage, 𝐴𝑘𝑙 and 𝐵𝑘𝑙 are templates of each cell, whose values represent the weights of synapses connecting two nearby cells, and 𝐼𝑖𝑗 is the input bias current of each cell. Due to its massive symmetric and identical structure with local connections, the CNN can be easily implemented with analog VLSI circuits using operational amplifiers and operational transconductance amplifiers (OTAs) as neurons and synapses [10-12]. The main drawbacks of this analog implementation are large area and power dissipation.
In this paper, we propose an alternative way to implement the CNN using single-domain nanomagnets to reduce the area and improve the energy efficiency. The basis of this approach is that a magnet can be switched by the spin transfer torque induced by a spin-polarized current [13]. The amplitude of the spin-polarized current determines the switching delay of the magnet, which essentially makes the magnet act as an integrator. The basic building block is adopted from the all-spin logic (ASL) [5], which was proposed as one of the beyond-CMOS device options for the Boolean logic computation. Recent results from a benchmarking study for a 32-bit adder implemented by various emerging computational devices have shown that ASL is orders of magnitude slower and more power-hungry compared to CMOS [2]. Here, however, we demonstrate that implementing CNN with ASL devices is much more efficient, and the improvement is shown to be application dependent. The rest of the paper is organized as follow

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