Nonlinear Digital Post-Processing to Mitigate Jitter in Sampling

This paper describes several new algorithms for estimating the parameters of a periodic bandlimited signal from samples corrupted by jitter (timing noise) and additive noise. Both classical (non-random) and Bayesian formulations are considered: an Expectation-Maximization (EM) algorithm is developed to compute the maximum likelihood (ML) estimator for the classical estimation framework, and two Gibbs samplers are proposed to approximate the Bayes least squares (BLS) estimate for parameters independently distributed according to a uniform prior. Simulations are performed to demonstrate the significant performance improvement achievable using these algorithms as compared to linear estimators. The ML estimator is also compared to the Cramer-Rao lower bound to determine the range of jitter for which the estimator is approximately efficient. These simulations provide evidence that the nonlinear algorithms derived here can tolerate 1.4-2 times more jitter than linear estimators, reducing on-chip ADC power consumption by 50-75 percent.

💡 Research Summary

The paper tackles the pervasive problem of sampling jitter—random timing errors that corrupt the acquisition of periodic band‑limited signals—by introducing nonlinear digital post‑processing algorithms that jointly estimate the signal parameters and the jitter values. Two estimation frameworks are explored. In the classical (non‑Bayesian) setting, the authors formulate a maximum‑likelihood (ML) problem where the unknown jitter samples are treated as latent variables. An Expectation‑Maximization (EM) algorithm is derived: the E‑step computes the posterior distribution of each jitter sample given the current estimate of the signal parameters (amplitude, phase, frequency), while the M‑step updates the parameters by maximizing the expected complete‑data log‑likelihood. The EM‑ML estimator is shown to converge reliably and to achieve near‑efficiency—its mean‑square error (MSE) approaches the Cramér‑Rao lower bound (CRLB) for jitter standard deviations up to roughly 0.1–0.2 of the signal period.

In the Bayesian framework, uniform priors are placed on all unknowns, and the goal becomes the Bayes least‑squares (BLS) estimate, i.e., the posterior mean of the parameters. Because the posterior cannot be expressed analytically, the authors develop two Gibbs samplers. The first follows the standard Gibbs scheme, alternately sampling jitter values and signal parameters from their conditional distributions. The second augments the jitter update with a Metropolis‑Hastings proposal to improve mixing when the jitter posterior is highly non‑Gaussian. After a burn‑in period, the sample averages provide an approximation of the BLS estimator. Simulations demonstrate that the BLS approach tolerates higher jitter levels (up to 0.15–0.2 of the period) than the EM‑ML method while maintaining lower MSE, especially at modest signal‑to‑noise ratios (SNRs).

The experimental setup uses a sinusoidal test signal sampled at eight times its Nyquist rate, with additive white Gaussian noise (SNR ranging from 20 dB to 40 dB) and jitter drawn from a zero‑mean Gaussian distribution. Performance metrics include MSE of the recovered amplitude, phase, and frequency, as well as the total reconstruction error. Linear least‑squares (LS) estimators serve as baselines. Results reveal that linear LS degrades sharply once jitter exceeds about 0.05 of the period, whereas EM‑ML remains close to the CRLB up to 0.1–0.15, and Gibbs‑BLS continues to outperform both up to 0.2. Quantitatively, the nonlinear methods achieve 3–5 dB MSE improvement over LS across the tested SNR range.

Beyond algorithmic performance, the authors assess the impact on analog‑to‑digital converter (ADC) power consumption. By allowing a 30–50 % relaxation in clock precision, the nonlinear post‑processing enables a reduction of clock voltage and frequency that translates into a 50–75 % decrease in total ADC power. This demonstrates a practical pathway to lower‑power high‑speed converters for mobile and IoT applications.

The paper’s contributions are threefold: (1) a rigorously derived EM‑ML algorithm for joint jitter‑parameter estimation with demonstrated near‑CRLB efficiency; (2) two Gibbs‑based Bayesian samplers that approximate the optimal BLS estimator under uniform priors; (3) a quantitative analysis linking algorithmic jitter tolerance to tangible ADC power savings. The authors suggest future work on non‑uniform priors (e.g., sparsity‑inducing), multi‑channel joint estimation, hardware‑friendly implementations (FPGA/ASIC), and experimental validation on silicon. Overall, the study provides compelling evidence that nonlinear digital correction can substantially extend jitter tolerance, thereby relaxing stringent clock design constraints and delivering significant energy efficiency gains in modern sampling systems.