Enabling Effective FPGA Debug using Overlays: Opportunities and Challenges

📝 Abstract

FPGAs are going mainstream. Major companies that were not traditionally FPGA-focused are now seeking ways to exploit the benefits of reconfigurable technology and provide it to their customers. In order to do so, a debug ecosystem that provides for effective visibility into a working design and quick debug turn-around times is essential. Overlays have the opportunity to play a key role in this ecosystem. In this overview paper, we discuss how an overlay fabric that allows the user to rapidly add debug instrumentation to a design can be created and exploited. We discuss the requirements of such an overlay and some of the research challenges and opportunities that need to be addressed. To make our exposition concrete, we use two previously-published examples of overlays that have been developed to implement debug instrumentation.

💡 Analysis

FPGAs are going mainstream. Major companies that were not traditionally FPGA-focused are now seeking ways to exploit the benefits of reconfigurable technology and provide it to their customers. In order to do so, a debug ecosystem that provides for effective visibility into a working design and quick debug turn-around times is essential. Overlays have the opportunity to play a key role in this ecosystem. In this overview paper, we discuss how an overlay fabric that allows the user to rapidly add debug instrumentation to a design can be created and exploited. We discuss the requirements of such an overlay and some of the research challenges and opportunities that need to be addressed. To make our exposition concrete, we use two previously-published examples of overlays that have been developed to implement debug instrumentation.

📄 Content

Enabling Effective FPGA Debug using Overlays: Opportunities and Challenges Fatemeh Eslami1, Eddie Hung2, and Steven J.E. Wilton1 1Department of Electrical and Computer Engineering 2Department of Electrical and Electronic Engineering University of British Columbia, Vancouver, Canada Imperial College London, London, U.K. {feslami,stevew}@ece.ubc.ca e.hung@imperial.ac.uk Abstract—FPGAs are going mainstream. Major companies that were not traditionally FPGA-focused are now seeking ways to exploit the benefits of reconfigurable technology and provide it to their customers. In order to do so, a debug ecosystem that provides for effective visibility into a working design and quick debug turn-around times is essential. Overlays have the opportunity to play a key role in this ecosystem. In this overview paper, we discuss how an overlay fabric that allows the user to rapidly add debug instrumentation to a design can be created and exploited. We discuss the requirements of such an overlay and some of the research challenges and opportunities that need to be addressed. To make our exposition concrete, we use two previously-published examples of overlays that have been developed to implement debug instrumentation. I. INTRODUCTION The past several decades have seen tremendous growth in the capacity and capability of Field-Programmable Gate Arrays (FPGAs). Today, FPGAs are poised to enter the mainstream as compute accelerators, as evidenced by Intel’s recent acqui- sition of Altera and Microsoft’s public efforts to bring FPGA technology into the cloud [1]. For FPGAs to be successful in this new role, an entire design ecosystem is required. Traditional hardware designers may be willing to accept long design and debug cycles, however, application designers using FPGA technology to accelerate software applications may not. These designers may expect software-like compile times, and similar support for debug and optimization. In recent years, the concept of an overlay has emerged as a promising technology to provide this capability, and may become key to ensuring that FPGA technology is successful as it moves to the mainstream. Several researchers have described how overlays can ac- celerate the design and compile time of FPGA designs, either providing an embedded processor-style fabric which can be programmed using software [2], [3], or a flexible fabric and a compilation infrastructure that can quickly map circuits to the fabric [4], [5], [6], [7]. In some cases, the infrastructure is specifically optimized for accelerator-type circuits [8] or collections of small processing units [9]. Compiling a design, however, is only half the battle [10]. Designers also need an effective mechanism to debug and optimize their designs. Although many bugs can be found through simulation, many of the most elusive and troublesome bugs can only be found by running the design on an actual FPGA. When incorrect behaviour in a running chip is ob- served, finding the root cause of the behaviour is complicated by a lack of observability and controllability. Controllability Figure 1: Overview of our approach and observability can be added by including commercial or academic debug instrumentation [11], [12], [13], [14], [15], [16], [17], [18]. This instrumentation often records the run- time behaviour of selected signals in the chip, allowing it to be played back later using debug tools. Some degree of controllability is also provided; in [18], the user can single- step through code and set breakpoints. Most of these debug flows, however, require the design to be recompiled every time the instrumentation is changed. For very large designs, this can be prohibitive (often called a “go home event”) which can severely limit debug productivity. Further, recompiling a design may often lead to slightly different timing behaviour which may cause a bug to disappear or change. Incremental compilation techniques may accelerate compilation and reduce timing variability. However, because these are general-purpose techniques — in that they are de- signed to accelerate changes being made to the original circuit, as opposed to simply adding new read-only instrumentation — this can still be slow, especially if significant changes to the debug instrumentation are made. Overlays can provide a solution. An overlay can provide a flexible, adaptable, but generic fabric which can be compiled with the design once, and then used to implement debug instrumentation as shown in Figure 1. As the instrumentation is changed at debug time, the overlay can be reconfigured rapidly without changing the underlying user circuit. Unlike a typical overlay, this overlay can be optimized not only for debugging- type applications, but also for the underlying user circuit on a circuit-by-circuit basis. In this paper, we will describe the use of overlays op- timized to implement debug instrumentation. We will argue that our approach can lead to significant debug productivity Copyright held by the owner/

This content is AI-processed based on ArXiv data.