OpenRISC System-on-Chip Design Emulation

📝 Abstract

Recently the hardware emulation technique has emerged as a promising approach to accelerating hardware verification/debugging process. To fully evaluate the powerfulness of the emulation approach and demonstrate its potential impact, we propose to emulate a system-on-chip (SoC) design using Mentor Graphics Veloce emulation platform. This article presents our project setup and the results we have achieved. The results are encouraging. ORPSoC emulation with Veloce has more than ten times faster than hardware simulation. Our experimental results demonstrate that Mentor Graphics Veloce has major advantages in emulation, verification, and debugging of complicated real hardware designs, especially in the context of SoC complexity. Through our three major tasks, we will demonstrate that (1) Veloce can successfully emulate large-scale SoC designs; (2) it has much better performance comparing to the state-of-the-art simulation tools; (3) it can significantly accelerate the process of hardware verification and debugging while maintaining full signal visibility.

💡 Analysis

Recently the hardware emulation technique has emerged as a promising approach to accelerating hardware verification/debugging process. To fully evaluate the powerfulness of the emulation approach and demonstrate its potential impact, we propose to emulate a system-on-chip (SoC) design using Mentor Graphics Veloce emulation platform. This article presents our project setup and the results we have achieved. The results are encouraging. ORPSoC emulation with Veloce has more than ten times faster than hardware simulation. Our experimental results demonstrate that Mentor Graphics Veloce has major advantages in emulation, verification, and debugging of complicated real hardware designs, especially in the context of SoC complexity. Through our three major tasks, we will demonstrate that (1) Veloce can successfully emulate large-scale SoC designs; (2) it has much better performance comparing to the state-of-the-art simulation tools; (3) it can significantly accelerate the process of hardware verification and debugging while maintaining full signal visibility.

📄 Content

2014 Veloce Emulation Competition Report

OpenRISC System-on-Chip Design Emulation Kai Cong, Li Lei, and Zhenkun Yang Advisor: Fei Xie
{congkai, leil, zhenkun, xie}@cs.pdx.edu Department of Computer Science, Portland State University, Portland, OR

1. Introduction New computer systems like smartphones and tablets, are entering the market at an

ever-accelerating pace. This brings enormous pressure on the product development

teams to shorten the time-to-market. Driven by increasing design complexity and

decreasing time-to-market, it demands innovative approaches to accelerating hardware

design simulation, verification, and debugging. Recently the hardware emulation

technique has emerged as a promising approach to accelerating hardware

verification/debugging process.

To fully evaluate the powerfulness of the emulation approach and demonstrate its

potential impact, we propose to emulate a system-on-chip (SoC) design using Mentor

Graphics Veloce emulation platform. This article presents our project setup and the

results we have achieved. In this project, we carry out the following tasks: (1)

standalone emulation of an existing open-source SoC design, OpenRISC Reference

Platform System on Chip (ORPSoC); (2) emulation performance evaluation with three

categories of benchmarks, running ‘sum’ program with different parameters over

ORPSoC, booting the Linux kernel over ORPSoC and running a set of software

programs over ORPSoC; (3) thoroughly comparison with the simulation approach:

simulating ORPSoC with the benchmarks on Mentor Graphics ModelSim.

The results are encouraging. ORPSoC emulation with Veloce has more than ten times

faster than hardware simulation. Our experimental results demonstrate that Mentor

Graphics Veloce has major advantages in emulation, verification, and debugging of

complicated real hardware designs, especially in the context of SoC complexity.

Through our three major tasks, we will demonstrate that (1) Veloce can successfully

emulate large-scale SoC designs; (2) it has much better performance comparing to the

state-of-the-art simulation tools; (3) it can significantly accelerate the process of

hardware verification and debugging while maintaining full signal visibility.
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2014 Veloce Emulation Competition Report

2. Background OpenRISC 1200: OpenRISC 1200 (OR1200) [1] is a synthesizable CPU core

developed and maintained by developers at OpenCores [2]. The OR1200 design is an

open source implementation of the OpenRISC 1000 RISC architecture [3], which is

implemented in Verilog HDL. OR1200 has following major features:
● Central CPU/DSP block ● Direct mapped data/instruction cache ● WISHBONE bus interfaces

ORPSoC: ORPSoC is an OpenRISC-based reference SoC [4], which consists of

following hardware components, as shown in Figure 1. ● WISHBONE Bus ● SRAM Memory ● General-purpose I/O (GPIO) ● UART serial port ● 10/100Mbps Ethernet MAC

Figure-1: Architecture of ORPSoC with major components

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2014 Veloce Emulation Competition Report

3. ORPSoC Simulation We use Mentor Graphics ModelSim as our RTL design simulator. The workflow of our simulation is depicted as Figure-2.

Figure-2: Workflow of ORPSoC Simulation with ModelSim

The workflow contains three steps:
1). By using the OpenRISC compiler, the target program running on ORPSoC is

compiled into a memory file which is consumed by the simulator ModelSim. 2). ModelSim takes the compiled ORPSoC design and the memory file. It simulates the

target program running on the ORPSoC design.
3). ModelSim stops when the program terminates. It outputs the waveform of the

selected signals of the ORPSoC design and records the program output in the log

file.

4. ORPSoC Emulation 4.1 Workflow of ORPSoC Emulation. The workflow of our ORPSoC emulation with Mentor Graphics Veloce is illustrated as

Figure-3. In this workflow, the memory file generated from the target program plays as

the testbench which includes a significant amount of CPU instructions on our ORPSoC

design. 3

2014 Veloce Emulation Competition Report

Figure-3: Workflow of ORPSoC emulation with Veloce

The workflow contains four steps:
1). Using the OpenRISC co

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