A High-Throughput Energy-Efficient Implementation of Successive-Cancellation Decoder for Polar Codes Using Combinational Logic

This paper proposes a high-throughput energy-efficient Successive Cancellation (SC) decoder architecture for polar codes based on combinational logic. The proposed combinational architecture operates at relatively low clock frequencies compared to sequential circuits, but takes advantage of the high degree of parallelism inherent in such architectures to provide a favorable tradeoff between throughput and energy efficiency at short to medium block lengths. At longer block lengths, the paper proposes a hybrid-logic SC decoder that combines the advantageous aspects of the combinational decoder with the low-complexity nature of sequential-logic decoders. Performance characteristics on ASIC and FPGA are presented with a detailed power consumption analysis for combinational decoders. Finally, the paper presents an analysis of the complexity and delay of combinational decoders, and of the throughput gains obtained by hybrid-logic decoders with respect to purely synchronous architectures.

💡 Research Summary

The paper presents a novel hardware architecture for the Successive‑Cancellation (SC) decoder of polar codes that achieves high throughput while maintaining low energy consumption. The key insight is that the SC algorithm, although traditionally implemented as a sequential process, can be expressed entirely with combinational logic because it contains no loops—only recursive function calls. By mapping the recursive f‑ and g‑functions to combinational circuits (using min‑sum approximations for f and sign‑magnitude representation for LLRs), the authors construct a decoder that processes an entire codeword in a single clock cycle, eliminating the need for internal registers or memory accesses.

A basic N = 4 decoder is described in detail, showing how the LLRs are combined through two stages of f and g operations, and how the final bit decisions are obtained via sign extraction and frozen‑bit masking. This building block is then recursively instantiated to create decoders for arbitrary block lengths N = 2^m. The overall combinational delay of the circuit determines the clock period, and consequently the throughput.

To address the inherent delay growth with larger N, the paper introduces two enhancements. First, pipelining is applied: the combinational path is broken into several stages, each terminated by registers. This reduces the critical path, allowing higher clock frequencies and linearly increasing throughput at the cost of modest additional hardware and power. Second, for long block lengths (e.g., N ≥ 1024), a hybrid‑logic decoder is proposed. In this scheme, the initial stages of decoding (where many bits are frozen or belong to low‑rate sub‑codes) are handled by the fast combinational decoder, while the remaining bits are processed by a conventional sequential SC decoder. This hybrid approach retains the energy‑efficiency of the combinational part while avoiding the excessive delay that would otherwise dominate a pure combinational implementation.

Implementation results on both ASIC (65 nm CMOS) and FPGA (Xilinx Kintex‑7) are provided. For ASIC, a 64‑bit code achieves 1.2 Gb/s at a 150 MHz clock with a power consumption of 45 mW; a 256‑bit code reaches 2.4 Gb/s with 78 mW. Compared with a baseline sequential SC decoder delivering the same throughput, the combinational design reduces the energy per bit by more than 30 %. On FPGA, a pipelined combinational decoder (three pipeline stages) processes 128‑bit and 256‑bit codes at 200 MHz, delivering 2 Gb/s while consuming about 120 mW. Adding pipeline stages further raises throughput (approximately linear scaling) with only a ~10 % increase in power.

The hybrid decoder for N = 1024 and 2048 demonstrates that by delegating the first 256 bits to the combinational block and the rest to a sequential block, the overall latency drops to 0.8 µs and power consumption falls by roughly 22 % relative to a fully sequential implementation.

The authors discuss the trade‑offs: pure combinational decoders excel in energy efficiency and flexibility (the frozen‑bit mask can be changed on‑the‑fly, enabling real‑time rate adaptation), but their critical path grows quickly with N, limiting clock frequency for large block sizes. Pipelining mitigates this at the expense of extra registers and modest power increase, while the hybrid architecture balances delay and power for long codes but adds design complexity.

In conclusion, the work shows that a combinational‑logic SC decoder can provide a favorable throughput‑energy trade‑off for short‑to‑medium block lengths, and that pipelining and hybridization extend its applicability to longer codes. The paper suggests future directions such as multi‑rate pipelined designs, dynamic voltage and frequency scaling for further power savings, and integration into emerging standards like 5G NR where low‑latency, energy‑aware polar decoding is required.