Automatic Nested Loop Acceleration on FPGAs Using Soft CGRA Overlay

Offloading compute intensive nested loops to execute on FPGA accelerators have been demonstrated by numerous researchers as an effective performance enhancement technique across numerous application domains. To construct such accelerators with high design productivity, researchers have increasingly turned to the use of overlay architectures as an intermediate generation target built on top of off-the-shelf FPGAs. However, achieving the desired performance-overhead trade-off remains a major productivity challenge as complex application-specific customizations over a large design space covering multiple architectural parameters are needed. In this work, an automatic nested loop acceleration framework utilizing a regular soft coarse-grained reconfigurable array (SCGRA) overlay is presented. Given high-level resource constraints, the framework automatically customizes the overlay architectural design parameters, high-level compilation options as well as communication between the accelerator and the host processor for optimized performance specifically to the given application. In our experiments, at a cost of 10 to 20 minutes additional tools run time, the proposed customization process resulted in up to 5 times additional speedup over a baseline accelerator generated by the same framework without customization. Overall, when compared to the equivalent software running on the host ARM processor alone on the Zedboard, the resulting accelerators achieved up to 10 times speedup.

💡 Research Summary

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The paper presents an automatic nested‑loop acceleration framework that builds on a soft coarse‑grained reconfigurable array (SCGRA) overlay placed on commercial FPGAs. The authors target the productivity bottleneck of FPGA development by introducing an intermediate overlay layer that enables rapid compilation, bitstream reuse, and portable designs. However, overlays typically incur performance and resource overheads; therefore, the framework automatically customizes the overlay architecture, high‑level compilation options, and host‑accelerator communication to meet user‑specified resource constraints while maximizing performance for a given application.

The design space is defined by three groups of parameters: (1) loop compilation factors—unrolling factor u and grouping factor g, (2) overlay configuration—SCGRA topology (fixed 2‑D torus), array dimensions r × c, data width, and sizes of input/output buffers and address buffers, and (3) fixed hardware characteristics such as operation set, clock frequency, and pipeline depth. Using analytical models that exploit the regularity of the SCGRA, the authors can accurately estimate DFG compute time, DMA communication latency, and FPGA resource consumption (LUT, FF, DSP, BRAM) for any configuration C.

The optimization problem is formulated as minimizing total run time (compute time plus communication time) subject to resource and memory constraints. Because the compute time depends primarily on the unrolling factor and SCGRA size, a two‑step exploration is employed. First, a sub‑design‑space‑exploration (sub‑DSE) searches the (u, r, c) space to find configurations that sharply reduce loop execution time. Then, given this reduced feasible set, the remaining parameters (grouping factor, buffer sizes, etc.) are tuned to satisfy the constraints. The analytical models allow each candidate to be evaluated in milliseconds, making the entire customization process complete within 10–20 minutes—over 100× faster than exhaustive search.

The framework, named QuickDough, integrates a fast accelerator generation path that can instantiate a basic SCGRA‑based accelerator in seconds using a pre‑built bitstream library. The customization path produces an application‑specific overlay and driver, which are then stored in the accelerator library for future rapid reuse.

Experimental validation on a Xilinx Zynq‑7000 (ZedBoard) platform shows that the customized accelerators achieve up to 5× speedup over the baseline QuickDough accelerator (which lacks application‑specific tuning) and up to 10× speedup compared with the same kernels executed on the ARM Cortex‑A9 processor alone. The authors demonstrate this across several benchmarks, including matrix multiplication, FIR filtering, and image processing kernels. Resource usage is kept within the available BRAM, DSP, LUT, and FF budgets, confirming that the overlay can be sized just enough for the target application.

In summary, the work delivers a practical solution to the FPGA productivity‑performance trade‑off: by leveraging a regular SCGRA overlay and analytical performance models, it automatically derives near‑optimal hardware configurations for nested‑loop kernels with modest tool runtime. Future directions include extending the methodology to handle more complex control flow, multi‑kernel workloads, and dynamic runtime reconfiguration for adaptive performance scaling.