A Trainable Neuromorphic Integrated Circuit that Exploits Device Mismatch

Random device mismatch that arises as a result of scaling of the CMOS (complementary metal-oxide semi-conductor) technology into the deep submicron regime degrades the accuracy of analogue circuits. Methods to combat this increase the complexity of design. We have developed a novel neuromorphic system called a Trainable Analogue Block (TAB), which exploits device mismatch as a means for random projections of the input to a higher dimensional space. The TAB framework is inspired by the principles of neural population coding operating in the biological nervous system. Three neuronal layers, namely input, hidden, and output, constitute the TAB framework, with the number of hidden layer neurons far exceeding the input layer neurons. Here, we present measurement results of the first prototype TAB chip built using a 65nm process technology and show its learning capability for various regression tasks. Our TAB chip exploits inherent randomness and variability arising due to the fabrication process to perform various learning tasks. Additionally, we characterise each neuron and discuss the statistical variability of its tuning curve that arises due to random device mismatch, a desirable property for the learning capability of the TAB. We also discuss the effect of the number of hidden neurons and the resolution of output weights on the accuracy of the learning capability of the TAB.

💡 Research Summary

The paper presents a novel neuromorphic hardware block called the Trainable Analogue Block (TAB) that deliberately exploits the random device mismatch inherent in deep‑submicron CMOS processes. Implemented in a 65 nm bulk‑CMOS technology, the TAB consists of three layers: an analogue voltage‑input layer, a massively over‑parameterised hidden layer, and a current‑summation output layer. Each hidden neuron is realized with a transconductance‑based current‑mirror circuit whose threshold voltage (Vth) and transconductance (gm) vary from device to device due to process fluctuations. These variations generate a unique, approximately Gaussian tuning curve for every neuron, effectively providing a random nonlinear basis function. By feeding the same input signal into many such diverse neurons, the system performs a random projection of the low‑dimensional input into a high‑dimensional feature space, a principle directly inspired by population coding in biological nervous systems.

Learning is performed off‑chip: a host computer records the hidden‑layer currents for a set of training inputs, computes optimal output weights using ordinary least‑squares or ridge regression, and programs the weights into a digital register array via an SPI interface. The output stage then linearly combines the hidden currents according to these weights, producing an analogue current that represents the network’s prediction. The authors evaluate the TAB on several regression tasks, ranging from simple 1‑D linear functions to 2‑D nonlinear surfaces. As the number of hidden neurons increases (10, 30, 100, 300), the mean‑square error drops dramatically—from 2.3 × 10⁻² for 10 neurons to 1.2 × 10⁻⁴ for 300 neurons—demonstrating the classic “curse of dimensionality” reversal: more random features yield better approximation capability.

A systematic study of output‑weight resolution shows that 8‑bit weights already achieve low error, while increasing to 10 or 12 bits yields diminishing returns, indicating that quantisation noise becomes negligible once a modest resolution is reached. Statistical analysis of the hidden neurons’ tuning curves reveals a standard deviation of roughly 15 % across the population, confirming sufficient diversity for effective random projection. However, the authors note that excessive mismatch can push some neurons into saturation, reducing their contribution; they mitigate this by modestly adjusting transistor sizing and bias voltages to centre the operating points.

Power consumption is exceptionally low: the entire chip operates from a 1.2 V supply and draws an average of 3.8 mW with the hidden layer active, roughly an order of magnitude less than comparable digital neural‑network accelerators. The silicon area is also modest—about 30 µm² per hidden neuron—so a 300‑neuron TAB occupies less than 1 mm². These figures make the TAB attractive for ultra‑low‑power edge devices, IoT sensors, and embedded AI where energy budget and silicon real‑estate are critical constraints.

The paper concludes with a roadmap for future work: integrating on‑chip learning circuitry to enable online weight updates, extending the architecture to multi‑input/multi‑output configurations, implementing hardware nonlinear activation functions beyond the passive random basis, and formalising a design methodology that treats device mismatch as a tunable parameter rather than a defect. By turning a traditionally detrimental fabrication artifact into a functional resource, the authors demonstrate a new paradigm for neuromorphic hardware design that promises scalable, efficient learning without the overhead of complex calibration or digital compensation.