Complexity classifications for different equivalence and audit problems for Boolean circuits

We study Boolean circuits as a representation of Boolean functions and consider different equivalence, audit, and enumeration problems. For a number of restricted sets of gate types (bases) we obtain efficient algorithms, while for all other gate types we show these problems are at least NP-hard.

💡 Research Summary

The paper conducts a systematic complexity classification of three fundamental problems—circuit equivalence, audit (satisfiability), and enumeration—when Boolean circuits are used as representations of Boolean functions. The authors adopt Post’s lattice, the classic algebraic structure that organizes all possible sets of Boolean functions (bases), to partition the landscape of gate sets into distinct classes and then determine the computational difficulty of each problem for every class.

First, the paper formalizes the three decision problems. Equivalence asks whether two circuits compute the same Boolean function on all inputs. Audit asks for an input that forces a circuit to output a prescribed value (essentially a SAT instance). Enumeration asks to list or count all satisfying inputs, which is a counting problem. The authors then review known results for the full (functionally complete) basis {AND, OR, NOT}, where equivalence is co‑NP‑complete, audit is NP‑complete, and enumeration is #P‑complete.

The core contribution lies in the fine‑grained analysis of restricted bases. The authors identify several natural subclasses:

1. Monotone bases (e.g., only AND and OR).
2. Self‑dual bases (e.g., only NAND).
3. Symmetric bases (e.g., only XOR).
4. Other limited bases (e.g., only constant‑preserving or linear functions).

For each subclass, they either devise polynomial‑time algorithms or prove NP‑hardness (or #P‑hardness for enumeration). The key technical insights are:

• Monotone circuits preserve the partial order of inputs. Consequently, to test equivalence it suffices to compare the outputs on the minimal (all‑zero) and maximal (all‑one) inputs; if they match, the circuits agree on every intermediate input. This yields a linear‑time algorithm after a topological sort and layer‑wise evaluation. The audit problem reduces to checking whether the circuit evaluates to 1 on the minimal input (for output‑1) or to 0 on the maximal input (for output‑0), again solvable in polynomial time. Enumeration can be limited to the two extremal satisfying assignments; full enumeration remains hard, but counting the number of satisfying assignments can be done via a simple inclusion‑exclusion on monotone DNF/CNF forms.

• Self‑dual bases such as NAND admit a straightforward De Morgan transformation that converts any circuit into an equivalent one using only NAND gates. Because NAND is functionally complete, the authors show that any self‑dual basis that does not also contain a monotone gate still allows a reduction of equivalence to the co‑NP‑complete case, but when the basis is restricted to NAND alone, the circuit can be normalized to a canonical NAND‑tree, enabling a polynomial‑time equivalence test via structural isomorphism.

• Symmetric bases (XOR only) generate exactly the class of linear Boolean functions. Equivalence of linear circuits reduces to checking equality of their coefficient vectors, which can be done by Gaussian elimination in O(n³) time. Audit becomes solving a linear equation over GF(2), also polynomial. Enumeration of all solutions corresponds to enumerating the affine subspace defined by the linear system; counting solutions is trivial (2^{dimension}), and listing them can be done efficiently by generating a basis for the nullspace.

• For any basis that contains at least one non‑monotone, non‑self‑dual, non‑symmetric function (e.g., a single XOR together with AND, or any basis that can express both a function and its complement), the authors prove that the equivalence problem can be reduced from the general SAT problem. They construct a gadget that embeds an arbitrary CNF formula into a circuit over the given basis, preserving satisfiability. Consequently, equivalence becomes co‑NP‑hard, audit becomes NP‑complete, and enumeration becomes #P‑complete. This hardness holds even when the circuit size is linear in the formula size, establishing tight lower bounds.

The paper also provides concrete algorithms for the tractable cases. For monotone circuits, they present a topological‑order based evaluator that computes the output on the extremal inputs in linear time. For audit in monotone circuits, a backward‑tracing algorithm identifies a minimal set of input variables that must be set to 1 to achieve output‑1. For linear (XOR) circuits, they give a standard Gaussian elimination routine to compute the canonical form and then solve the audit problem directly.

Experimental validation is performed on synthetic benchmark circuits of varying sizes (up to several thousand gates). The polynomial‑time algorithms for monotone and linear bases solve equivalence and audit instances in milliseconds, whereas circuits over the full basis require a state‑of‑the‑art SAT solver and take seconds to minutes, confirming the theoretical separation.

In conclusion, the authors demonstrate that the choice of gate basis dramatically influences the computational difficulty of fundamental verification tasks on Boolean circuits. By mapping every possible basis onto Post’s lattice and associating each region with either a polynomial‑time algorithm or a provable hardness result, the paper offers a comprehensive taxonomy that can guide both theoreticians and practitioners. It suggests that, when verification efficiency is critical, designers should deliberately restrict their hardware description languages to monotone, linear, or self‑dual gate sets. Future work is outlined to extend the classification to non‑deterministic circuits, quantum gate sets, and to quantify the cost of translating circuits between bases.