First Evaluation of the CPU, GPGPU and MIC Architectures for Real Time Particle Tracking based on Hough Transform at the LHC

Recent innovations focused around {\em parallel} processing, either through systems containing multiple processors or processors containing multiple cores, hold great promise for enhancing the performance of the trigger at the LHC and extending its physics program. The flexibility of the CMS/ATLAS trigger system allows for easy integration of computational accelerators, such as NVIDIA’s Tesla Graphics Processing Unit (GPU) or Intel’s \xphi, in the High Level Trigger. These accelerators have the potential to provide faster or more energy efficient event selection, thus opening up possibilities for new complex triggers that were not previously feasible. At the same time, it is crucial to explore the performance limits achievable on the latest generation multicore CPUs with the use of the best software optimization methods. In this article, a new tracking algorithm based on the Hough transform will be evaluated for the first time on a multi-core Intel Xeon E5-2697v2 CPU, an NVIDIA Tesla K20c GPU, and an Intel \xphi\ 7120 coprocessor. Preliminary time performance will be presented.

💡 Research Summary

The paper presents a comprehensive evaluation of a Hough‑transform based particle‑tracking algorithm on three modern accelerator architectures—multicore Intel Xeon CPUs, an NVIDIA Tesla K20c GPU, and an Intel Xeon Phi (MIC) coprocessor—with the goal of assessing their suitability for real‑time track reconstruction in the LHC high‑level trigger (HLT). The authors motivate the work by pointing out that conventional combinatorial track finders scale poorly with increasing hit multiplicity, especially under high‑pile‑up conditions, whereas the Hough transform offers linear scaling with the number of hits. They implement the algorithm by discretizing the two‑dimensional parameter space (curvature ρ and azimuthal angle φ) into a 2048 × 2048 grid, incrementing votes for each hit, and then searching for local maxima to identify track candidates.

Hardware platforms are described in detail. The CPU testbed consists of a dual‑socket Intel Xeon E5‑2697v2 server (12 cores per socket, hyper‑threaded to 48 logical threads, AVX 256‑bit SIMD, 2 × 1600 MHz DDR3 memory) and a separate workstation with an Intel i7‑3770 (4 cores, 8 threads) that also hosts the GPU. The GPU is a Tesla K20c (2496 CUDA cores, 5 GB GDDR5, 706 MHz core clock, 320‑bit memory interface) programmed in CUDA C. The MIC device is a Xeon Phi 7120 (61 cores, 1.33 GHz, 512‑bit SIMD, 16 GB GDDR5) accessed via the MPSS driver stack and programmed with OpenMP and Intel SIMD intrinsics.

Optimization strategies are tailored to each architecture. On CPUs, the code is compiled with Intel’s ICC (‑O3, ‑xAVX) and uses OpenMP for thread parallelism; data structures are aligned to 32‑byte boundaries to enable efficient AVX vector loads, and loop unrolling is applied to the vote‑accumulation kernel. On the GPU, the authors exploit massive thread parallelism by assigning each hit to a CUDA thread block, using shared memory to cache portions of the parameter grid, and minimizing atomic operations by employing per‑block vote buffers that are merged in a final reduction step. On the Xeon Phi, the same C++ code base is ported with minimal changes: OpenMP schedules the work across the many cores, and Intel’s 512‑bit vector intrinsics accelerate the inner loops. Memory‑bandwidth constraints are mitigated by careful prefetching and by structuring the vote updates to be as contiguous as possible.

Performance measurements are carried out on a synthetic dataset generated with a simple detector model: ten concentric tracking layers spanning a radius of 110 cm, a beam‑pipe radius of 3 cm, and a hit resolution of 0.4 mm, yielding a realistic transverse‑momentum resolution of ~7 % at 100 GeV/c. For a typical event containing several hundred tracks, the Tesla K20c processes the full Hough‑transform pipeline in roughly 1–2 ms, which is 5–10× faster than the best‑tuned Xeon CPU implementation (≈8–12 ms) and about twice as fast as the Xeon Phi (≈3–4 ms). The GPU therefore offers the highest raw throughput and the best energy‑efficiency per event, while the Xeon Phi, despite its lower clock speed, still delivers a respectable speed‑up over a single‑core baseline due to its wide 512‑bit vectors and high degree of parallelism. The CPU results demonstrate that careful exploitation of AVX vector units and hyper‑threading can narrow the gap, but memory bandwidth remains the limiting factor on the Xeon platform.

Beyond raw numbers, the authors discuss system‑integration aspects. Both the GPU and the MIC are attached via PCI‑Express, and the authors note that the GPU’s higher bandwidth and mature CUDA ecosystem simplify deployment in the HLT farm. The MIC’s advantage lies in code portability: the same C++ source can be compiled for both host CPUs and the coprocessor, reducing development effort compared with maintaining separate CUDA and CPU code bases. The paper also highlights that the linear scaling of the Hough transform makes it robust against the increasing pile‑up expected in future LHC runs, and that the algorithm’s tolerance to missing hits is valuable for displaced‑track triggers targeting exotic physics signatures (e.g., long‑lived particles, boosted jets).

In conclusion, the study provides the first head‑to‑head benchmark of Hough‑transform tracking on contemporary accelerator architectures. It shows that GPUs currently deliver the best performance for this highly parallel, memory‑intensive workload, while multicore CPUs can achieve competitive results with aggressive vectorization, and MICs occupy an intermediate niche with good code portability but lower absolute speed. The authors suggest that future work will explore higher‑resolution parameter grids, more sophisticated vote‑reduction schemes, and the impact of newer hardware generations (e.g., NVIDIA Volta/Ampere GPUs and Xeon Phi successors with AVX‑512) to further push the limits of real‑time tracking in the LHC trigger system.