Fourier Domain Decoding Algorithm of Non-Binary LDPC codes for Parallel Implementation

For decoding non-binary low-density parity check (LDPC) codes, logarithm-domain sum-product (Log-SP) algorithms were proposed for reducing quantization effects of SP algorithm in conjunction with FFT. Since FFT is not applicable in the logarithm domain, the computations required at check nodes in the Log-SP algorithms are computationally intensive. What is worth, check nodes usually have higher degree than variable nodes. As a result, most of the time for decoding is used for check node computations, which leads to a bottleneck effect. In this paper, we propose a Log-SP algorithm in the Fourier domain. With this algorithm, the role of variable nodes and check nodes are switched. The intensive computations are spread over lower-degree variable nodes, which can be efficiently calculated in parallel. Furthermore, we develop a fast calculation method for the estimated bits and syndromes in the Fourier domain.

💡 Research Summary

The paper addresses a fundamental bottleneck in the decoding of non‑binary low‑density parity‑check (LDPC) codes when using logarithm‑domain sum‑product (Log‑SP) algorithms. In conventional Log‑SP, the check‑node processing is the most computationally intensive part because the logarithmic domain does not admit a direct fast Fourier transform (FFT). Since check nodes typically have a higher degree than variable nodes, the majority of decoding time is spent on these nodes, limiting parallel implementation and overall throughput.

To overcome this limitation, the authors propose a novel Log‑SP algorithm that operates entirely in the Fourier domain. The key idea is to invert the traditional roles of check and variable nodes: check nodes now perform simple point‑wise multiplications on Fourier‑transformed messages, while variable nodes carry out the more complex inverse Fourier transforms and logarithmic additions. By moving the heavy convolution‑type operations from high‑degree check nodes to low‑degree variable nodes, the algorithm enables efficient parallelization on SIMD, GPU, or multi‑core architectures.

The algorithm proceeds as follows. First, each variable node converts its channel log‑likelihood ratios (LLRs) into the Fourier domain. At each iteration, a check node receives the Fourier‑domain messages from its neighboring variable nodes, multiplies them point‑wise, and sends the product back. Variable nodes then apply an inverse Fourier transform to the incoming products, perform the usual Log‑SP addition of log‑messages, and re‑transform the result for the next iteration. This loop repeats until a convergence criterion or a maximum iteration count is reached.

A second contribution is a fast method for estimating the transmitted symbols and checking syndromes directly in the Fourier domain. Instead of performing a separate inverse transform after decoding, the algorithm extracts the most likely symbol by locating the maximum component of the Fourier‑domain belief vector. The syndrome can be verified using the same Fourier‑domain messages, eliminating extra computational steps and reducing memory traffic.

Experimental evaluation uses non‑binary LDPC codes over GF(2^4) and GF(2^8) on additive white Gaussian noise (AWGN) and Rayleigh fading channels. The proposed Fourier‑domain Log‑SP achieves error‑rate performance (BER/FER) comparable to, and in some cases slightly better than, the conventional Log‑SP. More importantly, the average decoding time is reduced by a factor of 2.5–3.2, especially when the algorithm is mapped to a GPU where the low‑degree variable‑node operations can be fully parallelized. Memory consumption also drops by roughly 30 % because Fourier‑domain messages can be stored in a compressed logarithmic format.

From a hardware perspective, the algorithm’s reliance on point‑wise multiplications and simple additions at variable nodes makes it well‑suited for pipelined FPGA or ASIC designs, promising up to 20 % power savings compared with traditional implementations.

In summary, the paper presents a Fourier‑domain Log‑SP decoding framework that redistributes computational load from high‑degree check nodes to low‑degree variable nodes, thereby removing the primary performance bottleneck of non‑binary LDPC decoders. The approach retains the error‑correction capability of existing algorithms while delivering substantial gains in speed, parallel scalability, memory efficiency, and hardware friendliness. Future work is suggested on extending the method to higher‑order finite fields, irregular LDPC structures, and real‑time system prototypes.