Reed-Muller Realization of X (mod P)

This article provides a novel technique of X (mod P) realization. It is based on the Reed-Muller polynomial expansion. The advantage of the approach concludes in the capability to realize X (mod P) for an arbitrary P. The approach is competitive with the known realizations on the speed processing. Advantages and results of comparison with the known approaches for X [9:1] and P=7 is demonstrated.

💡 Research Summary

The paper introduces a novel hardware‑oriented method for computing the modular reduction operation X mod P by exploiting Reed‑Muller (RM) polynomial expansion. Traditional approaches such as Montgomery, Barrett, shift‑and‑subtract, or LUT‑based implementations either require multiple clock cycles, are tailored to specific moduli, or suffer from large area and power overhead when the modulus changes. In contrast, the RM‑based technique treats the modular reduction as a Boolean function of the input bits and rewrites it as a sum‑of‑products over GF(2). The authors first express each output bit of the result (⌈log₂ P⌉ bits) as a Boolean expression derived from the definition of modular reduction. They then apply a fast Möbius transform to obtain the Reed‑Muller coefficients, which correspond directly to AND‑gate terms. By eliminating redundant terms and minimizing the algebraic degree, the resulting network consists solely of 2‑input AND gates feeding into XOR trees, enabling a fully combinational implementation that can be evaluated in a single clock cycle.

The methodology is described in detail, including pseudocode for coefficient generation, term pruning, and mapping to hardware primitives. The authors emphasize that the process is fully automatic for any integer modulus P, making the approach scalable to arbitrary applications.

A concrete case study with a 9‑bit dividend (X =