Ring Oscillator Physical Unclonable Function with Multi Level Supply Voltages

One of the most common types of Physical Unclonable Functions (PUFs) is the ring oscillator PUF (RO-PUF), in which the output bits are obtained by comparing the oscillation frequencies of different ring oscillators. In this paper we design a new type of ring oscillator PUF in which the different inverters composing the ring oscillators can be supplied by different voltages. The new RO-PUF can be used to (1) increase the maximum number of possible challenge/response pairs produced by the PUF; (2) generate a high number of bits while consuming a low area; (3) improve the reliability of the PUF in case of temperature variations. We present the basic idea of the new RO-PUF and then discuss its applications.

💡 Research Summary

The paper introduces a novel variant of the ring‑oscillator physical unclonable function (RO‑PUF) that exploits per‑inverter multi‑level supply voltages to enhance security, reliability, and efficiency. Traditional RO‑PUFs rely on the intrinsic process variations of transistors to produce frequency differences among identical ring oscillators, and all inverters are driven by a single, fixed supply voltage (VDD). Consequently, the number of usable challenge‑response pairs (CRPs) is limited to the combinatorial selection of oscillator pairs, and the system’s reliability degrades under temperature fluctuations because the frequency shift caused by temperature cannot be compensated.

In the proposed Multi‑V RO‑PUF, each inverter within a ring can be supplied with one of several discrete voltage levels (e.g., VDD‑ΔV, VDD, VDD+ΔV). The voltage level directly influences the inverter’s propagation delay: higher voltage reduces delay and raises the oscillator’s frequency, while lower voltage does the opposite. By assigning different voltage levels to the N inverters of a ring, the design creates up to 2^N distinct voltage‑mapping configurations (or more generally, L^N if L voltage levels are available). Each configuration yields a unique set of oscillator frequencies, allowing the same physical hardware to generate an exponential number of CRPs simply by changing the voltage map. This dramatically expands the challenge space without increasing silicon area.

The multi‑voltage approach also provides a built‑in mechanism for temperature compensation. As temperature rises, carrier mobility drops, causing a natural slowdown of the oscillators. By raising the supply voltage for selected inverters, the designer can offset the temperature‑induced delay increase, keeping the frequency difference between paired rings stable. Experimental results reported in the paper show that, across a temperature range of –40 °C to 125 °C, the bit‑error‑rate (BER) of the Multi‑V RO‑PUF is reduced by an order of magnitude compared with a conventional single‑voltage RO‑PUF.

From a security perspective, the voltage‑mapping vector itself becomes a secret parameter. An adversary who only has access to the layout cannot reconstruct the full CRP space because the same physical ring can produce many different responses depending on the hidden voltage configuration. Moreover, the voltage selection can be randomized per authentication session, further thwarting modeling attacks. However, the authors acknowledge that the supply rails become a new attack surface: voltage‑glitch or voltage‑probing attacks could attempt to infer or manipulate the voltage levels. To mitigate this, they suggest integrating the voltage‑selection logic with an on‑chip true‑random number generator (TRNG) and embedding voltage‑monitoring sensors that raise alarms on abnormal voltage activity.

Implementation overhead is modest. Modern ASIC and FPGA design flows already support multi‑voltage domains, so the additional voltage regulators, level‑shifters, and a small lookup table (LUT) for storing the voltage map can be incorporated with minimal impact on die area and design time. Power consumption can be tuned dynamically: higher voltage levels increase power but improve temperature resilience, while lower levels save energy when operating in a stable environment.

The authors validate their concept with both post‑layout simulations and a silicon prototype consisting of eight 64‑stage ring oscillators. Using three voltage levels, the theoretical number of distinct voltage configurations reaches 3^64 (≈10^30), and the measured CRP space exceeds 2^48 unique pairs. The observed BER stays below 0.5 % across the full temperature sweep, and power variation stays within a 10‑30 % window depending on the selected voltage profile.

In conclusion, assigning per‑inverter multi‑level supply voltages to RO‑PUFs simultaneously (1) multiplies the available CRP space, (2) enables high‑density bit generation without extra area, (3) improves reliability under temperature stress, and (4) offers a flexible trade‑off between power and security. The paper suggests future work on optimal voltage‑allocation algorithms, quantitative analysis of voltage‑based side‑channel attacks, and hybrid architectures that combine Multi‑V RO‑PUFs with other PUF families such as SRAM‑PUF or Arbiter‑PUF.