Efficient Hardware Design and Implementation of Encrypted MIPS Processor

The paper describes the design and hardware implementation of 32-bit encrypted MIPS processor based on MIPS pipeline architecture. The organization of pipeline stages in such a way that pipeline can be clocked at high frequency. Encryption and Decryption blocks of data encryption standard (DES) cryptosystem and dependency among themselves are explained in detail with the help of block diagram. In order to increase the processor functionality and performance, especially for security applications we include three new instructions 32-bit LKLW, LKUW and CRYPT. The design has been synthesized at 40nm process technology targeting using Xilinx Virtex-6 device. The encrypted MIPS pipeline processor can work at 218MHz at synthesis level and 744MHz at simulation level.

💡 Research Summary

The paper presents the design, hardware implementation, and performance evaluation of a 32‑bit encrypted MIPS processor that integrates a Data Encryption Standard (DES) core into the classic five‑stage MIPS pipeline (Instruction Fetch, Decode, Execute, Memory, Write‑Back). The authors modify the pipeline to fetch 64‑bit encrypted instruction blocks from instruction memory, pass them through a DES decryption core, and then split the resulting two 32‑bit instructions for normal pipeline processing. The program counter is incremented by 8 bytes instead of the usual 4 to accommodate the 64‑bit block size.

To support cryptographic operations, three new instructions are introduced: LKLW (Load Key Lower Word), LKUW (Load Key Upper Word), and CRYPT. LKLW and LKUW are I‑type load‑word variants that load the lower and upper 32‑bit halves of a 64‑bit symmetric key into a dedicated key register in the decode stage. The CRYPT instruction is a J‑type command that takes a single Boolean argument; a non‑zero value enables encryption for subsequent instructions, while zero disables it. Because loading the key and enabling encryption can create data hazards, the authors insert NOPs between the key‑load instructions and the CRYPT command, and they adapt the existing forwarding and hazard‑detection units to handle these cases without altering the fundamental pipeline control logic.

In the Execute stage, the ALU operates as in a conventional MIPS processor, but when the second operand originates from the register file and the crypt signal is asserted, the data is routed through the DES encryption core before being written to memory. The Memory stage therefore contains both a DES encryption core (for data writes) and a DES decryption core (for data reads), together with multiplexers and demultiplexers that select between encrypted and plaintext paths based on control signals.

The entire processor is described in VHDL at the RTL level. Functional verification is performed both at block level (directed and random testbenches) and at top level (assembly program execution). The authors synthesize the design for a 40 nm Xilinx Virtex‑6 FPGA (XC6VLX240T‑3FF1156). Post‑synthesis reports show a clock period of 4.584 ns (≈218 MHz) and a simulated clock period of 1.343 ns (≈744 MHz). Resource utilization occupies roughly 20 % of the available slices, and power consumption is reported to be about 15 % lower than comparable implementations on earlier FPGA families.

Simulation results demonstrate correct decryption of encrypted instruction streams and correct encryption of data values. An example program loads a key (“KIRATPAL” in ASCII), enables encryption, processes an array, and stores the resulting ciphertext at memory address 56. The ciphertext matches the expected DES output for the given plaintext and key, confirming functional correctness.

The paper concludes that integrating a symmetric‑key cryptographic core directly into the MIPS pipeline yields a high‑performance, secure processor suitable for embedded applications where data confidentiality is required. The authors acknowledge that DES is no longer considered secure and suggest future work replacing the DES core with an AES core, further pipeline optimizations, and exploring dynamic key management to enhance both security and performance.