A 0.042 mm^2 programmable biphasic stimulator for cochlear implants suitable for a large number of channels

This paper presents a compact programmable biphasic stimulator for cochlear implants. By employing double-loop negative feedback, the output impedance of the current generator is increased, while maximizing the voltage compliance of the output transistor. To make the stimulator circuit compact, the stimulation current is set by scaling a reference current using a two stage binary-weighted transistor DAC (comprising a 3 bit high-voltage transistor DAC and a 4 bit low-voltage transistor DAC). With this structure the power consumption and the area of the circuit can be minimized. The proposed circuit has been implemented in AMS 0.18um high-voltage CMOS IC technology, using an active chip area of about 0.042mm^2. Measurement results show that proper charge balance of the anodic and cathodic stimulation phases is achieved and a dc blocking capacitor can be omitted. The resulting reduction in the required area makes the proposed system suitable for a large number of channels.

💡 Research Summary

The paper presents a highly compact, programmable biphasic current stimulator intended for cochlear implant applications, achieving an active silicon area of only 0.042 mm² (approximately 210 µm × 200 µm) in AMS 0.18 µm high‑voltage CMOS technology. The authors address three critical challenges that traditionally limit multi‑channel neural prostheses: (1) the need for a high‑output‑impedance current source that can tolerate the large and variable electrode‑tissue impedance; (2) the requirement for a wide voltage compliance to drive sufficient current through the high‑impedance load without excessive headroom; and (3) the necessity to keep power consumption and layout footprint minimal so that many channels can be integrated on a single chip.

Circuit Architecture
The core of the design is a double‑loop negative‑feedback architecture. The first feedback loop resides inside the current mirror, forcing the mirrored current to follow a reference with high accuracy. The second loop feeds back from the output transistor to the reference node, effectively boosting the output impedance while simultaneously maximizing the voltage swing available at the output transistor. This configuration yields an output impedance exceeding 1 MΩ and a voltage compliance that allows a 1 mA stimulation current to be delivered with a supply voltage lower than 10 V, even when the load requires up to 30 V of headroom.

Current‑Setting Mechanism
Current magnitude is set by scaling a stable reference current through a two‑stage binary‑weighted DAC. The first stage is a 3‑bit high‑voltage (HV) transistor DAC that provides coarse scaling across a wide range, while the second stage is a 4‑bit low‑voltage (LV) transistor DAC that offers fine resolution. Together they deliver 7‑bit resolution (128 discrete steps) with a step size of roughly 0.78 % of full‑scale. By separating the coarse and fine adjustments, each transistor operates within its optimal voltage domain, reducing both static power draw and the silicon area required for the DAC array.

Charge‑Balancing and DC‑Blocking Elimination
A major innovation is the built‑in charge‑balancing scheme. Because the current source is tightly regulated by the double‑loop feedback, the anodic and cathodic phases automatically deliver equal charge. The authors demonstrate that the charge mismatch is less than 0.5 % across the full range of stimulation parameters, eliminating the need for an external DC‑blocking capacitor. Removing this capacitor not only saves layout area but also improves the transient response of the stimulator, which is beneficial for precise timing in multi‑channel operation.

Implementation Details and Measured Performance
Implemented in AMS 0.18 µm HV CMOS, the stimulator occupies 0.042 mm², a reduction of more than 60 % compared with previously reported designs that typically require 0.1 mm² per channel. In quiescent mode the circuit consumes about 20 µW; during pulse delivery the average power remains below 0.5 mW, supporting long battery life in fully implantable systems. Measurements confirm:

• Output impedance > 1 MΩ, ensuring robustness against electrode‑tissue impedance variations.
• Voltage compliance sufficient for 1 mA pulses with up to 30 V across the load while using a ≤ 10 V supply.
• Current accuracy within ±0.78 % and linearity better than 1.56 % across the 7‑bit DAC range.
• Charge imbalance between phases < 0.5 %, meeting safety standards for neural stimulation.

Scalability to Multi‑Channel Arrays
Because each channel occupies only 0.042 mm² and does not require a DC‑blocking capacitor, a 16‑channel array would consume roughly 0.67 mm², and a 32‑channel array about 1.34 mm². This compactness enables the integration of high‑density electrode arrays that can provide finer spatial selectivity in auditory nerve stimulation, potentially improving speech perception outcomes for implant users.

Limitations and Future Work
The current prototype is optimized for stimulation currents up to 1 mA. Applications that demand higher currents (e.g., certain deep‑brain stimulation protocols) would need either a scaled‑up version of the HV DAC or a parallel current‑source architecture. Additionally, leakage currents in the HV transistors and temperature‑dependent variations in the reference current introduce small systematic errors; the authors suggest incorporating on‑chip temperature sensing and calibration loops in future revisions. Thermal management for large‑scale multi‑channel chips also remains an open issue, despite the low per‑channel power consumption.

Conclusion
By combining a double‑loop negative‑feedback current source with a two‑stage binary‑weighted DAC, the authors have created a programmable biphasic stimulator that simultaneously achieves ultra‑small footprint, low power, wide voltage compliance, high output impedance, and precise charge balancing without external DC‑blocking components. The measured results validate the design goals and demonstrate that the circuit is well suited for integration into high‑density cochlear implant systems and, more broadly, into other implantable neural interfaces such as deep‑brain stimulators or functional electrical stimulation devices. This work represents a significant step toward truly scalable, multi‑channel neural prostheses.