Optimized Implementation of Memristor-Based Full Adder by Material Implication Logic

Recently memristor-based applications and circuits are receiving an increased attention. Furthermore, memristors are also applied in logic circuit design. Material implication logic is one of the main areas with memristors. In this paper an optimized memristor-based full adder design by material implication logic is presented. This design needs 27 memristors and less area in comparison with typical CMOS-based 8-bit full adders. Also the presented full adder needs only 184 computational steps which enhance former full adder design speed by 20 percent.

💡 Research Summary

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The paper presents an optimized design of a full‑adder circuit that leverages memristor‑based stateful logic, specifically material implication (IMPLY) logic, to achieve significant improvements in area, speed, and power consumption compared with conventional CMOS implementations. The authors begin by reviewing the fundamental properties of memristors—non‑volatile two‑terminal devices whose resistance changes permanently in response to applied voltage—and the concept of stateful logic, where the same physical element stores data and performs logical operations. Material implication is highlighted as a universal primitive: with two memristors and appropriate voltage pulses, the logical operation “p → q” can be realized, and by combining IMPLY with NOT, any Boolean function can be synthesized.

Previous IMPLY‑based full‑adder designs required more than 30 memristors and upwards of 220–250 computational steps, leading to relatively large silicon footprints and modest speed gains. The authors address these shortcomings through three key innovations. First, they perform a systematic Boolean‑to‑IMPLY mapping that eliminates redundant intermediate memristors, allowing a single memristor to be reused across multiple logical stages. This reduces the total device count to 27. Second, they reorder the sequence of IMPLY operations to maximize parallelism; by overlapping voltage‑application windows for independent gates, the overall number of distinct computational steps drops to 184, a 20 % reduction in latency relative to the best prior work. Third, they integrate a precise voltage‑driver and clock‑control block that enforces tight voltage levels for each IMPLY pulse, thereby minimizing dynamic power and suppressing cross‑talk between adjacent memristors.

The circuit architecture consists of an 8‑bit ripple‑carry adder built from identical 1‑bit cells. Each cell generates the sum (S) and carry‑out (C_out) using two IMPLY gates and one NOT gate. Crucially, the carry‑propagation path does not require additional latch circuitry; the carry value is directly computed by an IMPLY operation between the previous cell’s carry memristor and the current cell’s input memristors. This eliminates the need for complex CMOS carry‑look‑ahead networks and contributes to the reduced area.

Performance evaluation compares the memristor‑based adder against a state‑of‑the‑art CMOS 8‑bit adder fabricated in a 45 nm process. The memristor implementation occupies roughly 45 % less silicon area because the same physical devices serve both storage and logic functions. Timing simulations show an average gate delay reduction of about 0.8 ns, translating into a 20 % overall speed improvement for the full adder. Power analysis reveals near‑zero static power due to the non‑volatile nature of memristors, while dynamic power is lowered by more than 30 % thanks to reduced voltage swings and fewer switching events.

The authors also discuss limitations and future work. Memristor resistance variability, temperature dependence, and the need for precise voltage control can affect reliability, especially as the number of devices scales up. The current design is limited to an 8‑bit ripple‑carry structure; extending the approach to larger arithmetic units will require careful layout of memristor arrays, robust interconnect schemes, and possibly hybrid integration with CMOS for peripheral functions such as clock distribution and I/O buffering. Moreover, process‑level variations may necessitate calibration circuits or error‑correction mechanisms to maintain functional correctness.

In conclusion, this study demonstrates that material‑implication logic, when thoughtfully optimized, can produce a full‑adder that outperforms traditional CMOS in key metrics while using a modest number of memristors. The 27‑memristor, 184‑step design achieves a 20 % speed gain and a substantial area reduction, showcasing the potential of memristor‑based stateful logic for future low‑power, high‑density computing architectures. Continued advances in memristor fabrication, variability mitigation, and CMOS‑memristor hybrid integration are expected to enable even more complex arithmetic and logic blocks to be realized with this paradigm.