FPGA design of a cdma2000 turbo decoder

📝 Original Info

• Title: FPGA design of a cdma2000 turbo decoder
• ArXiv ID: 1404.5929
• Date: 2014-04-24
• Authors: Researchers from original ArXiv paper

📝 Abstract

This paper presents the FPGA hardware design of a turbo decoder for the cdma2000 standard. The work includes a study and mathematical analysis of the turbo decoding process, based on the MAX-Log-MAP algorithm. Results of decoding for a packet size of two hundred fifty bits are presented, as well as an analysis of area versus performance, and the key variables for hardware design in turbo decoding.

💡 Deep Analysis

Deep Dive into FPGA design of a cdma2000 turbo decoder.

This paper presents the FPGA hardware design of a turbo decoder for the cdma2000 standard. The work includes a study and mathematical analysis of the turbo decoding process, based on the MAX-Log-MAP algorithm. Results of decoding for a packet size of two hundred fifty bits are presented, as well as an analysis of area versus performance, and the key variables for hardware design in turbo decoding.

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