Open Cores for Digital Signal Processing

This paper presents the design and implementation of three System on Chip (SoC) cores, which implement the Digital Signal Processing (DSP) functions: Finite Impulse Response (FIR) filter, Infinite Impulse Response (IIR) filter and Fast Fourier Transform (FFT). The FIR filter core is based on the symmetrical realization form, the IIR filter core is based on the Second Order Sections (SOS) architecture and the FFT core is based on the Radix $2^2$ Single Delay Feedback (R$2^2$SDF) architecture. The three cores are compatible with the Wishbone SoC bus and they were described using generic and structural VHDL. In system hardware verification was performed by using an OpenRisc-based SoC synthesized on an Altera FPGA, the tests showed that the designed DSP cores are suitable for building SoC based on the OpenRisc processor and the Wishbone bus.

💡 Research Summary

The paper presents a comprehensive design, implementation, and hardware verification of three digital signal processing (DSP) cores—Finite Impulse Response (FIR) filter, Infinite Impulse Response (IIR) filter, and Fast Fourier Transform (FFT)—targeted for integration into open‑source System‑on‑Chip (SoC) platforms. The authors adopt three well‑known algorithmic architectures that are particularly suited for resource‑constrained FPGA implementations. The FIR core uses a symmetric realization form, which exploits coefficient symmetry to halve the number of multiplications required. By structuring the datapath as a pipeline of input registers, a coefficient ROM, and a multiply‑accumulate (MAC) unit, the design achieves high clock frequencies while maintaining a modest logic footprint. The IIR core is based on the Second‑Order Sections (SOS) approach, which decomposes a high‑order filter into cascaded bi‑quadratic sections. Each section is implemented in Direct Form II, allowing for efficient scaling and overflow protection. The SOS architecture also improves numerical stability compared with a single high‑order direct form. The FFT core adopts the Radix‑2² Single Delay Feedback (R2²SDF) architecture. This scheme reduces memory requirements by roughly 50 % relative to a conventional Radix‑2 SDF while preserving the regular data‑flow pattern that is friendly to pipelining. A single delay line and a set of complex multiplication units are reused across stages, and twiddle factors are stored in a small ROM.

All three cores are wrapped with a Wishbone bus slave interface, providing a uniform address map, bus cycle handling, and optional interrupt signaling. The use of the Wishbone protocol ensures seamless integration with the OpenRISC processor, which serves as the master in the experimental SoC. The cores are described in generic, structural VHDL. Generics expose key parameters such as data width, filter order, number of SOS sections, and FFT point size, allowing designers to tailor the IP to specific application constraints without modifying the source code.

For validation, the authors synthesize an OpenRISC‑based SoC on an Altera Cyclone II FPGA, instantiate the three DSP cores, and connect them via the Wishbone interconnect. Functional verification is performed using both simulation testbenches and on‑board hardware tests. Input stimuli include white noise, sinusoidal tones, and real audio recordings. Output waveforms are compared against MATLAB reference models, confirming that the hardware implementations meet the expected frequency responses and spectral characteristics. Resource utilization is reported as approximately 12 % of the FPGA’s lookup tables (LUTs) for the FIR core, 8 % for the IIR core, and 15 % for the FFT core. All cores operate reliably at clock frequencies exceeding 150 MHz, demonstrating that the chosen architectures are compatible with high‑performance embedded DSP tasks. Power analysis using Altera’s Power Analyzer shows that the symmetric FIR and SOS‑based IIR achieve roughly 30 % and 25 % reductions in dynamic power compared with naïve implementations, primarily due to the reduced number of multipliers and the efficient scaling logic.

The paper concludes that the presented open‑source DSP cores provide a cost‑effective, high‑performance alternative to proprietary IP, while offering full configurability through VHDL generics and seamless bus compatibility. The authors suggest future work on extending the cores to support multi‑channel operation, higher‑precision floating‑point arithmetic, and porting to other bus standards such as AXI or Avalon. They also emphasize the potential for community‑driven enhancements and the value of these cores as educational tools for teaching digital signal processing and hardware design in open‑source environments.