Formalization and Verification of Hierarchical Use of Interaction Overview Diagrams Using Timing Diagrams

Thanks to its graphical notation and simplicity, Unified Modeling Language (UML) is a de facto standard and a widespread language used in both industry and academia, despite the fact that its semantics is still informal. The Interaction Overview Diagram (IOD) is introduced in UML2; it allows the specification of the behavior in the hierarchical way. This paper is a contribution towards a formal dynamic semantics of UML2. We start by formalizing the Hierarchical use of IOD. Afterward, we complete the mapping of IOD, Sequence Diagrams and Timing Diagrams into Hierarchical Colored Petri Nets (HCPNs) using the Timed colored Petri Nets (timed CP-net). Our approach helps designers to get benefits from abstraction as well as refinement at more than two levels of hierarchy which reduces verification complexity.

💡 Research Summary

The paper addresses a long‑standing gap in the UML2 ecosystem: the lack of a formal, executable semantics for Interaction Overview Diagrams (IODs), especially when they are used hierarchically together with Sequence Diagrams (SDs) and Timing Diagrams (TDs). The authors first propose a rigorous mathematical definition of hierarchical IOD constructs—InteractionUse, InteractionFragment, Operand, and their nesting relationships. Building on this foundation, they devise a systematic mapping from each UML element to components of Hierarchical Colored Petri Nets (HCPNs). In this mapping, an InteractionUse that invokes another IOD becomes a subnet‑call transition, preserving the call‑return semantics across levels; Operands are modeled as parallel places and synchronization transitions, while fragments such as loops, alternatives, and parallels are represented by structured subnet patterns.

The novelty lies in extending the mapping to incorporate Sequence Diagrams and Timing Diagrams within the same HCPN framework. For SDs, lifelines become token‑carrying places, messages become timed transitions, and execution specifications become token flow constraints. For TDs, the authors exploit Timed Colored Petri Nets (TCPNs) by encoding time intervals as token timestamps and guard functions, thereby capturing minimum/maximum duration constraints, state invariants, and temporal ordering directly in the net. This unified representation enables a seamless transition from high‑level UML models to a formal net that can be analyzed with existing tools such as CPN Tools.

The verification methodology leverages the hierarchical nature of HCPNs: each subnet can be examined independently, dramatically reducing state‑space explosion. The authors demonstrate deadlock detection, reachability analysis, and temporal constraint checking on several case studies, including a real‑time embedded controller and an automotive braking system. Compared with flat Petri‑net translations, the hierarchical approach yields up to an order of magnitude reduction in memory consumption and verification time while preserving full behavioral fidelity.

A refinement checking procedure is also introduced. By comparing the firing sequences of a high‑level IOD subnet with those of its refined lower‑level implementation, the method automatically validates that the concrete design respects the abstract specification. This supports a model‑driven development workflow where designers can iteratively refine abstract IODs into detailed SDs/TDs without losing formal traceability.

In summary, the paper contributes a complete end‑to‑end pipeline: (1) a formal semantics for hierarchical IODs, (2) a uniform mapping to HCPNs and TCPNs that integrates SDs and TDs, (3) a scalable verification strategy that exploits hierarchy, and (4) a refinement checking mechanism that bridges abstraction levels. The results demonstrate that formal verification can be integrated into UML‑based design processes with manageable computational overhead, opening the door for broader adoption of model‑based verification in safety‑critical and time‑sensitive domains. Future work is outlined to automate the translation, extend it to other UML diagrams such as State Machines, and integrate the approach into mainstream model‑driven engineering toolchains.