AND and/or OR: Uniform Polynomial-Size Circuits

We investigate the complexity of uniform OR circuits and AND circuits of polynomial-size and depth. As their name suggests, OR circuits have OR gates as their computation gates, as well as the usual input, output and constant (0/1) gates. As is the norm for Boolean circuits, our circuits have multiple sink gates, which implies that an OR circuit computes an OR function on some subset of its input variables. Determining that subset amounts to solving a number of reachability questions on a polynomial-size directed graph (which input gates are connected to the output gate?), taken from a very sparse set of graphs. However, it is not obvious whether or not this (restricted) reachability problem can be solved, by say, uniform AC^0 circuits (constant depth, polynomial-size, AND, OR, NOT gates). This is one reason why characterizing the power of these simple-looking circuits in terms of uniform classes turns out to be intriguing. Another is that the model itself seems particularly natural and worthy of study. Our goal is the systematic characterization of uniform polynomial-size OR circuits, and AND circuits, in terms of known uniform machine-based complexity classes. In particular, we consider the languages reducible to such uniform families of OR circuits, and AND circuits, under a variety of reduction types. We give upper and lower bounds on the computational power of these language classes. We find that these complexity classes are closely related to tallyNL, the set of unary languages within NL, and to sets reducible to tallyNL. Specifically, for a variety of types of reductions (many-one, conjunctive truth table, disjunctive truth table, truth table, Turing) we give characterizations of languages reducible to OR circuit classes in terms of languages reducible to tallyNL classes. Then, some of these OR classes are shown to coincide, and some are proven to be distinct. We give analogous results for AND circuits. Finally, for many of our OR circuit classes, and analogous AND circuit classes, we prove whether or not the two classes coincide, although we leave one such inclusion open.

💡 Research Summary

The paper investigates the computational power of uniform families of polynomial‑size Boolean circuits that are restricted to a single type of gate: either OR gates only (OR‑circuits) or AND gates only (AND‑circuits). Each circuit may contain multiple sink (output) gates, which means that an OR‑circuit computes the logical OR of some subset of its input variables, while an AND‑circuit computes the logical AND of a (possibly different) subset. The central technical observation is that determining which inputs influence a given output reduces to a reachability problem on a directed graph whose vertices correspond to gates and whose edges correspond to wiring. Because the circuits are of polynomial size and constant depth, the associated graphs are very sparse and have a highly constrained structure.

The authors ask whether this restricted reachability problem can be solved by uniform AC⁰ circuits (constant depth, polynomial size, with AND, OR, NOT gates). Answering this question allows them to place the OR‑ and AND‑circuit families within the landscape of well‑studied uniform complexity classes. Their main tool is a series of reductions between language classes: many‑one (Karp) reductions, conjunctive truth‑table (CTT) reductions, disjunctive truth‑table (DTT) reductions, general truth‑table (TT) reductions, and Turing reductions. By systematically analysing each reduction type, they relate languages that are reducible to uniform OR‑circuits (or AND‑circuits) to languages that are reducible to tallyNL – the set of unary languages that belong to NL.

Key results include:

1. Many‑one reductions – A language L is many‑one reducible to a uniform OR‑circuit family iff L is many‑one reducible to a language in tallyNL. Consequently, the class of languages many‑one reducible to OR‑circuits coincides exactly with the class of languages many‑one reducible to tallyNL. The same holds symmetrically for AND‑circuits.

2. Conjunctive truth‑table reductions – For OR‑circuits, the class of languages CTT‑reducible to them is identical to the class CTT‑reducible to tallyNL. This shows that the “all‑queries‑must‑accept” style of reduction does not increase power beyond tallyNL when the target is an OR‑circuit.

3. Disjunctive truth‑table reductions – The analogous statement holds for AND‑circuits and DTT reductions: languages DTT‑reducible to AND‑circuits are exactly those DTT‑reducible to tallyNL.

4. General truth‑table reductions – The authors prove one inclusion: every language TT‑reducible to a uniform OR‑circuit family is also TT‑reducible to tallyNL. The reverse inclusion remains open, leaving a gap in the characterization of TT‑reducible languages.

5. Turing reductions – Similar inclusions are established for Turing reductions, again showing that the computational power of uniform OR/AND circuits does not exceed that of tallyNL under these more powerful reductions, though full equivalence is not proved for all cases.

The proofs rely on two main ideas. First, the reachability problem inherent in an OR‑circuit can be simulated by a nondeterministic log‑space (NL) algorithm: a nondeterministic machine guesses a path from an input gate to the output sink and verifies it using only logarithmic workspace. Second, because the graph is polynomial‑size and the circuit depth is constant, the NL computation can be encoded as a unary language, placing it inside tallyNL. The authors then show how each reduction type can be transformed to operate on these unary encodings, preserving the reduction’s structure.

A notable contribution is the systematic comparison of the OR‑circuit and AND‑circuit worlds. By exploiting De Morgan duality, many results for OR‑circuits have direct analogues for AND‑circuits, and the paper presents these parallel theorems side by side.

The paper also highlights open problems. The most prominent is whether the reverse inclusion for general truth‑table reductions holds: does every language TT‑reducible to tallyNL also reduce (via a TT‑reduction) to a uniform OR‑circuit family? Resolving this would complete the picture for TT‑reductions. Additionally, the authors suggest that allowing logarithmic depth (instead of constant depth) or considering non‑uniform families could dramatically change the landscape, potentially moving the circuit classes up to NL or even P.

In summary, the work provides a thorough characterization of the computational capabilities of uniform polynomial‑size OR and AND circuits. By linking these seemingly simple circuit models to tallyNL through a variety of reduction notions, the authors demonstrate that the power of such restricted circuits is precisely captured by unary NL languages. The results deepen our understanding of how circuit uniformity, gate restrictions, and reduction types interact, and they open avenues for further exploration of sparse circuit models and their place in the broader complexity‑theoretic hierarchy.