A Satisfiability Algorithm for Sparse Depth Two Threshold Circuits

We give a nontrivial algorithm for the satisfiability problem for cn-wire threshold circuits of depth two which is better than exhaustive search by a factor 2^{sn} where s= 1/c^{O(c^2)}. We believe that this is the first nontrivial satisfiability algorithm for cn-wire threshold circuits of depth two. The independently interesting problem of the feasibility of sparse 0-1 integer linear programs is a special case. To our knowledge, our algorithm is the first to achieve constant savings even for the special case of Integer Linear Programming. The key idea is to reduce the satisfiability problem to the Vector Domination Problem, the problem of checking whether there are two vectors in a given collection of vectors such that one dominates the other component-wise. We also provide a satisfiability algorithm with constant savings for depth two circuits with symmetric gates where the total weighted fan-in is at most cn. One of our motivations is proving strong lower bounds for TC^0 circuits, exploiting the connection (established by Williams) between satisfiability algorithms and lower bounds. Our second motivation is to explore the connection between the expressive power of the circuits and the complexity of the corresponding circuit satisfiability problem.

💡 Research Summary

The paper tackles the satisfiability (SAT) problem for depth‑2 threshold circuits whose total number of wires is bounded by cn, where c is a constant. Such circuits consist of a layer of input variables feeding into a single layer of linear threshold gates; each gate computes a weighted sum of its inputs and outputs 1 if the sum exceeds a prescribed threshold, otherwise 0. Prior to this work, no algorithm was known that could beat the naïve exhaustive search of 2^{cn} time for this class, and even the special case of sparse 0‑1 integer linear programs (ILPs) lacked any constant‑factor speed‑up.

The authors’ main contribution is a non‑trivial SAT algorithm that runs in time 2^{(c‑s)n} with s = 1/c^{O(c²)}. In other words, the algorithm saves a factor of 2^{sn} over brute force, where s is a positive constant depending only on c. This is the first known algorithm to achieve a constant‑factor improvement for any cn‑wire depth‑2 threshold circuit, and consequently for sparse 0‑1 ILPs as a special case.

The key technical idea is to reduce the circuit‑SAT instance to the Vector Domination Problem. For each threshold gate the authors write the linear inequality that must be satisfied by a satisfying assignment. By considering all possible sign patterns of the input variables, they construct two families of vectors, A and B. Vectors in A encode the weighted sums of the inputs for each gate under a particular sign pattern, while vectors in B encode the corresponding thresholds (adjusted by the sign pattern). A satisfying assignment exists iff there is a pair (a ∈ A, b ∈ B) such that a dominates b component‑wise (i.e., a_i ≥ b_i for every coordinate i).

The Vector Domination Problem has been studied independently, and there exist algorithms that run in O(N^{2‑ε}) time for a collection of N vectors (for some ε > 0). The authors plug this algorithm directly into their reduction. Because the circuit has at most cn wires, the number of distinct sign patterns—and thus the size of the vector families—is bounded by N = 2^{O(cn)}. Substituting the known domination algorithm’s runtime yields the overall SAT running time 2^{cn}·2^{-sn} = 2^{(c‑s)n}. The exponent s is derived from the ε‑dependence on c, giving the explicit expression s = 1/c^{O(c²)}.

Beyond the basic reduction, the paper also handles symmetric gates—gates whose output depends only on the multiset of input values, not on their order. When the total weighted fan‑in (the sum of absolute values of all gate weights) is at most cn, the symmetry can be exploited to collapse many duplicate vectors, effectively reducing the dimensionality of the domination instance. This yields the same constant‑factor savings for a broader class of circuits that include symmetric gates.

A particularly noteworthy corollary is the application to sparse 0‑1 integer linear programs. An ILP with m constraints and n variables can be viewed as a depth‑2 threshold circuit where each constraint corresponds to a gate. If the total number of non‑zero coefficients (the sparsity) is bounded by cn, the reduction applies unchanged, giving a SAT algorithm for such ILPs that also enjoys a 2^{sn} speed‑up. To the best of the authors’ knowledge, this is the first algorithm that provides any constant‑factor improvement for ILP feasibility, even in the sparse regime.

The authors motivate their work from two angles. First, Williams’ connection between faster SAT algorithms and circuit lower bounds suggests that any non‑trivial SAT algorithm for a circuit class can be leveraged to prove strong lower bounds against that class. Consequently, the algorithm presented here opens a possible route to proving super‑polynomial lower bounds for depth‑2 threshold circuits (and by extension for the class TC⁰). Second, the paper explores how the expressive power of a circuit (e.g., presence of symmetry, fan‑in constraints) influences the computational difficulty of its SAT problem, offering a nuanced view of the interplay between circuit design and algorithmic tractability.

In summary, the paper delivers:

1. A reduction from depth‑2 cn‑wire threshold‑circuit SAT to the Vector Domination Problem.
2. An application of the best known domination algorithm to obtain a SAT runtime of 2^{(c‑s)n}, i.e., a 2^{sn} constant‑factor improvement over exhaustive search, with s = 1/c^{O(c²)}.
3. Extensions to circuits with symmetric gates under a total weighted fan‑in bound.
4. A direct corollary for sparse 0‑1 ILPs, achieving the first constant‑factor speed‑up for this problem.
5. Discussion of implications for TC⁰ lower bounds via Williams’ framework and insights into how circuit structure affects SAT complexity.

Overall, the work bridges a gap between circuit complexity and algorithm design, introducing a novel reduction technique and achieving the first meaningful SAT speed‑up for a natural class of sparse threshold circuits.