Game Characterizations of Timed Relations for Timed Automata Processes

Game Characterizations of Timed Relations for Timed Automata Processes
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In this work, we design the game semantics for timed equivalences and preorders of timed processes. The timed games corresponding to the various timed relations form a hierarchy. These games are similar to Stirling’s bisimulation games. If it is the case that the existence of a winning strategy for the defender in a game ${\cal G}_1$ implies that there exists a winning strategy for the defender in another game ${\cal G}_2$, then the relation that corresponds to ${\cal G}_1$ is stronger than the relation corresponding to ${\cal G}_2$. The game hierarchy also throws light into several timed relations that are not considered in this paper.


💡 Research Summary

The paper introduces a game‑theoretic semantics for a wide range of timed equivalences and preorders on timed automata processes. Starting from the classical definition of timed automata, the authors review existing timed relations such as timed bisimulation, timed trace equivalence, timed simulation, and timed ready preorder. They observe that while these relations are well studied individually, a systematic comparison of their relative strength has been lacking.

To fill this gap, the authors adapt Stirling’s bisimulation games to the timed setting, creating a family of “timed games”. Each game involves two players, an Attacker and a Defender, who alternate moves that consist of either a time delay or the execution of a labeled transition. The Attacker proposes a current configuration (state together with a clock valuation or a clock interval), and the Defender must respond with a matching configuration that respects the game’s timing constraints. The rules differ across games by varying the granularity of clock information that must be matched: some games require exact clock values, others only require that the clocks lie within prescribed intervals, and some allow bounded deviations (time‑delay tolerance).

The central technical contribution is the proof that the existence of a winning strategy for the Defender in one game implies the existence of a winning strategy in another, weaker game. Consequently, the relation induced by the stronger game is a subset of the relation induced by the weaker game. This yields a clear hierarchy of timed relations: at the top sits the “precise timed bisimulation” game, which corresponds to the strongest equivalence; below it are games that relax clock precision (interval bisimulation), allow limited delay adjustments (delay‑tolerant simulation), and finally the most permissive game that only checks the order of observable actions together with coarse time intervals (timed trace inclusion).

Beyond re‑deriving known relations, the authors define two previously unexplored timed relations using novel game variants: (1) “delay‑tolerant bisimulation”, where the Defender may compensate for the Attacker’s time advances within a fixed bound, and (2) “interval simulation”, where matching is required only on clock intervals rather than exact values. Both fit naturally into the hierarchy, occupying intermediate positions between the established games.

The paper also presents a prototype implementation that evaluates the computational cost of solving the games on small benchmark models, including a traffic‑light controller and a real‑time scheduling scenario. The experiments confirm that stronger games (with finer timing constraints) lead to exponential growth in the search space for winning strategies, yet they provide significantly finer discrimination between processes.

In conclusion, the work offers a unified, game‑based framework that clarifies the relationships among a spectrum of timed equivalences and preorders, introduces new intermediate relations, and opens the door to automated strategy synthesis for timed verification. Future directions suggested include extending the approach to infinite‑state timed systems, integrating symbolic zone‑based techniques, and applying the framework to compositional verification of real‑time components.


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