The decomposition of the regular asynchronous systems as parallel connection of regular asynchronous systems
The asynchronous systems are the non-deterministic models of the asynchronous circuits from the digital electrical engineering, where non-determinism is a consequence of the fact that modelling is made in the presence of unknown and variable parameters. Such a system is a multi-valued function f that assigns to an (admissible) input u:R{\to}{0,1}^{m} a set f(u) of (possible) states x:R{\to}{0,1}^{n}. When this assignment is defined by making use of a so-called generator function {\Phi}:{0,1}^{n}{\times}{0,1}^{m}{\to}{0,1}^{n}, then the asynchronous system f is called regular. The generator function {\Phi} acts in this asynchronous framework similarly with the next state function from a synchronous framework. The parallel connection of the asynchronous systems f’ and f" is the asynchronous system (f’||f")(u)=f’(u){\times}f"(u). The purpose of the paper is to give the circumstances under which a regular asynchronous system f may be written as a parallel connection of regular asynchronous systems.
💡 Research Summary
The paper investigates the mathematical foundations of regular asynchronous systems—non‑deterministic models that capture the behavior of asynchronous digital circuits under unknown or variable physical parameters. An asynchronous system is formalized as a multi‑valued mapping f that assigns to each admissible input signal u (a function u:ℝ→{0,1}ᵐ) a set of possible state trajectories x (a function x:ℝ→{0,1}ⁿ). When the assignment is generated by a deterministic “generator” function Φ:{0,1}ⁿ×{0,1}ᵐ→{0,1}ⁿ, the system is called regular. The generator function plays the same role as the next‑state function in synchronous design, but because transitions occur asynchronously, the exact timing of state updates is not fixed, leading to a set of admissible trajectories rather than a single trajectory.
The central question addressed is under what circumstances a regular system f can be expressed as the parallel connection of two (or more) regular subsystems f′ and f″. The parallel connection is defined pointwise by (f′‖f″)(u)=f′(u)×f″(u), where “×” denotes the Cartesian product of the state sets; both subsystems receive the same input u but evolve independently. The authors show that the necessary and sufficient condition for such a decomposition is a structural property of the generator function Φ: it must be block‑diagonal with respect to a partition of the state and input variables.
Formally, let the state index set N={1,…,n} be split into two disjoint subsets N′ and N″, and the input index set M={1,…,m} be split into M′ and M″. Write a state vector μ∈{0,1}ⁿ as μ=(μ′,μ″) and an input vector λ∈{0,1}ᵐ as λ=(λ′,λ″). The decomposition condition requires that for every (μ,λ),
Φ(μ,λ) = (Φ′(μ′,λ′), Φ″(μ″,λ″)),
where Φ′:{0,1}^{|N′|}×{0,1}^{|M′|}→{0,1}^{|N′|} and Φ″:{0,1}^{|N″|}×{0,1}^{|M″|}→{0,1}^{|N″|} depend only on their respective subsets. In other words, the next‑state of the variables in N′ is completely independent of the variables in N″ and of the inputs in M″, and vice‑versa. The paper proves that this block‑diagonal form is both necessary (if a decomposition exists, the generator must separate the variables) and sufficient (if the generator separates the variables, one can define regular subsystems f′ and f″ with generators Φ′ and Φ″, and their parallel connection reproduces f exactly).
Beyond the structural condition, the authors examine the preservation of non‑determinism. Because each subsystem may have its own asynchronous timing uncertainties, the overall system’s set of admissible trajectories is the Cartesian product of the subsystems’ trajectory sets. Consequently, the decomposition does not collapse the inherent nondeterminism; it merely distributes it across independent modules.
The paper discusses several implications for asynchronous circuit design. First, modular decomposition simplifies verification: each module can be analyzed in isolation, reducing the state‑space explosion typical of global analysis. Second, hardware implementation can benefit from independent optimization of power, area, and delay for each module, since the lack of cross‑dependence eliminates timing constraints between them. Third, the result provides a theoretical justification for hierarchical design methodologies that are common in synchronous design but have been less formalized for asynchronous systems.
Finally, the authors outline future research directions, including extensions to more than two modules, handling of dynamic reconfiguration where the partition of variables may change over time, and incorporation of probabilistic models of delay to capture stochastic aspects of asynchronous behavior. The work thus bridges a gap between abstract algebraic models of asynchronous computation and practical engineering concerns, offering a clear criterion—block‑diagonal generator functions—for when a complex regular asynchronous system can be cleanly split into parallel, regular components.