Graph Coloring Algorithms for Muti-core and Massively Multithreaded Architectures

We explore the interplay between architectures and algorithm design in the context of shared-memory platforms and a specific graph problem of central importance in scientific and high-performance computing, distance-1 graph coloring. We introduce two different kinds of multithreaded heuristic algorithms for the stated, NP-hard, problem. The first algorithm relies on speculation and iteration, and is suitable for any shared-memory system. The second algorithm uses dataflow principles, and is targeted at the non-conventional, massively multithreaded Cray XMT system. We study the performance of the algorithms on the Cray XMT and two multi-core systems, Sun Niagara 2 and Intel Nehalem. Together, the three systems represent a spectrum of multithreading capabilities and memory structure. As testbed, we use synthetically generated large-scale graphs carefully chosen to cover a wide range of input types. The results show that the algorithms have scalable runtime performance and use nearly the same number of colors as the underlying serial algorithm, which in turn is effective in practice. The study provides insight into the design of high performance algorithms for irregular problems on many-core architectures.

💡 Research Summary

The paper investigates how the characteristics of modern shared‑memory architectures influence the design of high‑performance algorithms for the distance‑1 graph coloring problem, a fundamental NP‑hard task that appears in many scientific and engineering applications such as mesh partitioning, register allocation, and parallel task scheduling. Two distinct multithreaded heuristic approaches are presented. The first, called Speculative Iterative Coloring (SIC), is a general‑purpose algorithm that can run on any shared‑memory system. It assigns colors to vertices in parallel, allowing threads to work speculatively; when a conflict (two adjacent vertices receiving the same color) is detected, the offending vertices are placed back into a work queue for re‑coloring in subsequent iterations. The design deliberately minimizes atomic operations and uses per‑thread local buffers to reduce cache line contention, thereby achieving good scalability on conventional multicore CPUs. The second approach, Dataflow‑Driven Coloring (DFC), is tailored to the Cray XMT, a massively multithreaded machine that supports hundreds of thousands of hardware threads and provides hardware‑level conflict resolution. DFC transforms the graph into streams of vertices and adjacency lists, builds a dataflow graph that encodes the color‑dependency constraints, and lets each node fire automatically when its inputs become available. This “on‑demand” execution eliminates unnecessary thread activation, balances load intrinsically, and exploits the XMT’s ability to tolerate massive concurrency without explicit synchronization.

Experimental evaluation is carried out on three platforms representing a spectrum of multithreading capabilities: the Cray XMT, Sun Niagara 2 (8 cores, 8 threads per core), and Intel Nehalem (8 cores, 2 threads per core). A suite of synthetic graphs of varying size (10⁶–10⁸ vertices, 10⁷–10⁹ edges) and topology (scale‑free, random, power‑grid, and real‑world network models) is used as the benchmark. The metrics considered are runtime, number of colors produced, scalability with respect to thread count, and memory bandwidth utilization. Results show that SIC scales almost linearly on Niagara 2 and Nehalem up to the point where memory bandwidth becomes the limiting factor; beyond that point performance plateaus, but the algorithm still produces colorings within 1–2 % of the sequential baseline. On the XMT, DFC exhibits continuous speed‑up as the number of active threads grows from 10⁴ to 10⁶, achieving up to a twelve‑fold reduction in execution time compared with the sequential algorithm while using less than 1 % more colors. Memory‑access analysis reveals that SIC’s local buffering improves L2 cache hit rates by roughly 15 %, whereas DFC benefits from the XMT’s hardware conflict‑avoidance, keeping bandwidth consumption below 70 % of peak. Load‑balancing observations indicate that SIC requires explicit work‑queue redistribution to avoid stragglers, while DFC’s dataflow model naturally distributes work across the massive thread pool.

The study concludes that algorithmic design must be tightly coupled to architectural features: speculative, iteration‑based methods work well on conventional multicore CPUs with limited hardware threads, whereas dataflow‑centric, conflict‑free designs unlock the potential of massively multithreaded machines. The authors suggest several avenues for future work, including extending the techniques to emerging memory technologies such as high‑bandwidth memory (HBM) and non‑volatile RAM, developing hybrid frameworks that combine the strengths of SIC and DFC for heterogeneous systems, and applying the methods to real scientific workloads (e.g., finite‑element meshes, electromagnetic simulations) to validate their practical impact.