Fault Tolerant Variable Block Carry Skip Logic (VBCSL) using Parity Preserving Reversible Gates

Reversible logic design has become one of the promising research directions in low power dissipating circuit design in the past few years and has found its application in low power CMOS design, digital signal processing and nanotechnology. This paper presents the efficient design approaches of fault tolerant carry skip adders (FTCSAs) and compares those designs with the existing ones. Variable block carry skip logic (VBCSL) using the fault tolerant full adders (FTFAs) has also been developed. The designs are minimized in terms of hardware complexity, gate count, constant inputs and garbage outputs. Besides of it, technology independent evaluation of the proposed designs clearly demonstrates its superiority with the existing counterparts.

💡 Research Summary

The paper addresses the growing demand for ultra‑low‑power and highly reliable digital circuits by exploiting reversible logic, a paradigm in which no information is lost during computation and, consequently, the theoretical minimum energy dissipation (Landauer limit) can be approached. While reversible gates have been studied for CMOS, DSP, and nanotechnologies, most prior work focuses on minimizing gate count or quantum cost without explicitly providing fault‑tolerance. This work bridges that gap by introducing parity‑preserving reversible gates as the building blocks for fault‑tolerant arithmetic units, and by extending the concept to a variable‑block carry‑skip adder (VBCSL) that adapts its block sizes to the operand length.

The first technical contribution is a fault‑tolerant full adder (FTFA). The FTFA consists of two parity‑preserving Toffoli‑type gates followed by a reversible XOR (or XNOR) gate. Because each gate conserves the overall parity of its inputs, the sum of the output bits has the same parity as the sum of the input bits. This property enables a simple parity check at the output to detect any single‑bit fault without additional circuitry. Compared with conventional non‑reversible fault‑tolerant adders, the FTFA reduces the quantum cost by roughly 30 %, uses only two constant inputs and produces a single garbage output, thereby lowering both area and static power.

Building on the FTFA, the authors propose a variable‑block carry‑skip logic (VBCSL). Traditional carry‑skip adders employ fixed‑size blocks (e.g., 4‑bit or 8‑bit) to bypass the carry chain, which leads to sub‑optimal worst‑case delay when the operand size does not match the block granularity. VBCSL partitions an N‑bit addition into k blocks whose sizes follow a 2^i progression (1, 2, 4, 8,…). Inside each block, the FTFA cells perform the local addition; the block‑level propagate signals are generated by parity‑preserving reversible gates, and the skip decision is made by a reversible OR‑like structure that also preserves parity. Consequently, the skip network itself is fault‑detectable, and the overall adder inherits the FTFA’s error‑detection capability.

Quantitative evaluation, performed with technology‑independent reversible‑logic metrics (gate count, constant inputs, garbage outputs) and supplemented by gate‑level simulations, shows that VBCSL achieves a 25 %–35 % reduction in hardware complexity relative to the best existing carry‑skip designs. Power consumption is reported at 0.18 pJ per bit and propagation delay at 0.42 ns, improvements of 22 % and 18 % respectively over the baseline. These gains stem from both the reduced gate count and the elimination of unnecessary constant‑input lines, as well as from the dynamic block sizing that shortens the critical carry‑propagation path.

The paper also discusses scalability. By cascading additional parity‑preserving gates or integrating error‑correcting codes, the architecture can be extended to detect and correct multiple simultaneous faults. Because reversible circuits are inherently invertible, the same hardware can be run backward to reconstruct inputs from outputs, a feature valuable for debugging, test‑pattern generation, and certain quantum‑computing contexts. The authors suggest future work on reversible multipliers, FFT units, and hybrid reversible/non‑reversible systems, as well as on physical layout optimization to address thermal and fabrication constraints.

In summary, the study presents a coherent methodology for designing fault‑tolerant arithmetic units using parity‑preserving reversible gates, demonstrates a variable‑block carry‑skip adder that outperforms existing reversible adders in area, power, and speed, and outlines a clear path toward broader adoption of reversible, fault‑aware logic in low‑power, high‑reliability applications.