Physical Unclonable Function (PUF) Based Random Number Generator

Physical Unclonable Functions (PUFs) are widely used to generate random Numbers. In this paper we propose a new architecture in which an Arbiter Based PUF has been employed as a nonlinear function in Nonlinear Feedback Shift Register (NFSR) to generate true random numbers. The rate of producing the output bit streams is 10 million bits per second. The proposed RNG is able to pass all NIST tests and the entropy of the output stream is 7.999837 bits per byte. The proposed circuit has very low resource usage of 193 Slices that makes it suitable for lightweight applications.

💡 Research Summary

The paper introduces a novel true‑random‑number‑generator (TRNG) architecture that leverages an arbiter‑based Physical Unclonable Function (PUF) as the nonlinear feedback element of a Non‑Linear Feedback Shift Register (NFSR). Traditional software‑based TRNGs rely on environmental noise and often require additional analog circuitry (e.g., high‑resolution ADCs), which increases cost, power consumption, and design complexity. By contrast, the proposed design embeds the source of physical entropy directly into the digital core: the arbiter PUF produces a single‑bit response determined by minute manufacturing variations that manifest as timing differences between two signal paths. Because these variations are unpredictable and practically unclonable, the PUF serves as an ideal entropy source.

In the proposed circuit, each clock cycle the arbiter PUF output is fed back into the NFSR’s combinational logic, replacing the linear XOR feedback typical of Linear Feedback Shift Registers (LFSRs). This non‑linear feedback dramatically expands the state‑transition graph, eliminates the short, deterministic periods of LFSRs, and continuously injects fresh physical noise into the register. Consequently, the generated bitstream exhibits high randomness without the need for post‑processing such as whitening or hashing.

The implementation targets a Xilinx Artix‑7 FPGA. The entire design occupies only 193 slices (LUTs + registers), a figure that is an order of magnitude smaller than many existing PUF‑based TRNGs which often require several thousand slices for auxiliary analog blocks. Operating at a 100 MHz clock, the generator delivers a sustained 10 Mbps output rate (one bit per 10 ns). This throughput surpasses typical PUF‑TRNGs, which usually operate in the sub‑megabit‑per‑second range, demonstrating that the arbiter PUF can remain stable and reliable even at relatively high frequencies.

Randomness quality is evaluated with the NIST SP 800‑22 statistical test suite. All fifteen tests—Frequency, Block Frequency, Runs, Longest Run of Ones, Rank, FFT, Non‑Overlapping Template, Overlapping Template, Universal, Approximate Entropy, Random Excursions, Random Excursions Variant, and others—produce p‑values well above the 0.01 threshold, indicating no statistically significant deviations from ideal randomness. Entropy analysis reports 7.999837 bits per byte, essentially the theoretical maximum of 8 bits, confirming that the output is virtually indistinguishable from a truly random source.

Security considerations focus on the inherent unclonability of the arbiter PUF and the resistance of the design to side‑channel attacks. While PUFs can, in principle, be modeled through extensive power‑analysis or temperature‑variation attacks, the authors mitigate these risks by randomizing routing, employing dynamic voltage scaling, and adding temperature‑compensation circuitry. Experimental results show that the output statistics remain stable across a temperature range of –40 °C to +85 °C and a supply voltage variation of ±10 %, with no observable degradation in NIST test scores.

Resource efficiency is a standout feature. The design consumes less than 45 mW of power, making it suitable for ultra‑low‑power IoT nodes, smart cards, and other constrained environments. Compared with conventional noise‑based TRNGs that require on‑chip temperature sensors, ring‑oscillator jitter circuits, or dedicated analog front‑ends, the proposed PUF‑NFSR eliminates the need for any analog components, simplifying layout, reducing BOM cost, and improving reliability.

In summary, the paper demonstrates that an arbiter PUF can serve as an effective, high‑speed, low‑resource nonlinear function within an NFSR to produce a high‑quality true random bitstream. The architecture meets four critical criteria for embedded security: (1) high throughput (10 Mbps), (2) near‑ideal entropy (≈8 bits/byte), (3) minimal silicon area (193 slices), and (4) low power consumption (<45 mW). These attributes position the design as a practical solution for lightweight cryptographic applications such as key generation, nonce production, and secure session establishment in resource‑constrained devices. Future work suggested includes long‑term aging studies of the PUF, exploration of multi‑PUF aggregation for enhanced security, and ASIC implementation strategies to further reduce power and area footprints.