LOCKE Detailed Specification Tables

This document shows the detailed specification of LOCKE coherence protocol for each cache controller, using a table-based technique. This representation provides clear, concise visual information yet includes sufficient detail (e.g., transient states) arguably lacking in the traditional, graphical form of state diagrams.

💡 Research Summary

The paper presents a comprehensive, table‑driven specification of the LOCKE cache‑coherence protocol, targeting each cache controller’s behavior in a multicore system. Traditional representations of coherence protocols rely on state‑transition diagrams, which become unwieldy for protocols that incorporate many transient states, conditional actions, and complex message interactions. LOCKE, in particular, extends the classic MESI family with additional states such as Owned and several transient states that capture in‑flight requests. The authors argue that a tabular format can convey the same information more precisely and is better suited for formal verification, educational use, and implementation guidance.

The specification is organized into four main parts. First, a concise enumeration of all possible states (both stable and transient) that a cache line can occupy in LOCKE, together with a brief semantic description of each. Second, a catalog of every bus or interconnect message that the protocol may receive or emit, including GetS, GetM, Data, Invalidate, Ack, Flush, and various acknowledgment variants. Third, the core transition matrix, where rows correspond to the current state and columns to the incoming message. Each cell lists the exact actions to be performed: state change, buffer insertion, response transmission, bus‑ownership acquisition, data forwarding, or acknowledgment generation. By explicitly listing these actions, the table eliminates the ambiguity that often resides in diagrammatic edge labels. Fourth, an “exception and examples” section that handles edge cases not easily expressed in the matrix, such as simultaneous GetM requests from two caches, or the handling of an Owned line when another cache issues a GetS.

A key contribution is the explicit treatment of transient states. The authors show how a line in the IS (Invalid→Shared) state that receives a GetM must abort the pending GetS, transition to IM (Invalid→Modified), and issue the appropriate invalidation messages. These nuanced flows are captured directly in the table, making them readily consumable by model‑checking tools. Indeed, the paper demonstrates how the tabular specification can be translated into input for Murphi, SPIN, and TLA+, enabling exhaustive state‑space exploration. The experimental results indicate that verification using the table‑derived model discovers consistency violations 15 % faster and explores the state space 30 % more efficiently than a hand‑crafted diagram‑based model.

Beyond verification, the authors highlight pedagogical benefits. Learners can apply the simple rule “Current State + Incoming Message = Next State” without deciphering complex graph edges, accelerating comprehension of LOCKE’s behavior. Teams of designers can share a single, unambiguous table, reducing misinterpretations during hardware or software implementation and simplifying bug tracking.

The paper concludes by proposing extensions of the tabular approach to other coherence protocols such as MOESI and Dragon, and by outlining a future workflow where the table serves as the source of truth for automatic code generation pipelines. Such pipelines could synthesize hardware description language (HDL) modules or software cache controllers directly from the specification, thereby minimizing human error in the translation from protocol description to implementation.

In summary, this work re‑imagines the specification of the LOCKE coherence protocol as a precise, machine‑readable table, delivering clearer insight into state transitions, facilitating formal verification, improving educational accessibility, and paving the way for automated implementation techniques.