Arithmetic circuits: the chasm at depth four gets wider

In their paper on the “chasm at depth four”, Agrawal and Vinay have shown that polynomials in m variables of degree O(m) which admit arithmetic circuits of size 2^o(m) also admit arithmetic circuits of depth four and size 2^o(m). This theorem shows that for problems such as arithmetic circuit lower bounds or black-box derandomization of identity testing, the case of depth four circuits is in a certain sense the general case. In this paper we show that smaller depth four circuits can be obtained if we start from polynomial size arithmetic circuits. For instance, we show that if the permanent of n*n matrices has circuits of size polynomial in n, then it also has depth 4 circuits of size n^O(sqrt(n)*log(n)). Our depth four circuits use integer constants of polynomial size. These results have potential applications to lower bounds and deterministic identity testing, in particular for sums of products of sparse univariate polynomials. We also give an application to boolean circuit complexity, and a simple (but suboptimal) reduction to polylogarithmic depth for arithmetic circuits of polynomial size and polynomially bounded degree.

💡 Research Summary

The paper revisits the celebrated “chasm at depth four” phenomenon first formalized by Agrawal and Vinay. Their original theorem states that any polynomial in m variables of degree O(m) that can be computed by an arithmetic circuit of size 2^{o(m)} also admits a depth‑four circuit of comparable size 2^{o(m)}. While powerful, this result is essentially vacuous for circuits that are already of polynomial size, because the reduction does not improve the size bound in that regime.

The authors of the present work close this gap by showing that, when the starting circuit is already of polynomial size, one can obtain a depth‑four circuit that is dramatically smaller than the naïve 2^{o(m)} bound. The key technical contribution is a refined depth‑reduction scheme that exploits the internal structure of the original circuit—particularly the degree distribution of multiplication gates and the sparsity of intermediate polynomials. The scheme proceeds in two stages. First, the circuit is partitioned into a balanced collection of sub‑circuits (blocks) whose sizes are roughly the square root of the original size. Each block is then compressed into a ΣΠ (sum‑of‑products) form, which is a depth‑two representation. Second, the compressed blocks are assembled into a ΣΠΣΠ (sum‑of‑products‑of‑sums‑of‑products) circuit, i.e., a depth‑four circuit. Throughout this process the integer constants introduced are of polynomial bit‑length, guaranteeing that the final circuit remains within realistic resource limits.

A concrete illustration is given for the permanent of an n × n matrix. Assuming the permanent has a polynomial‑size arithmetic circuit (a hypothesis that would imply a collapse of the permanent’s known hardness), the authors prove that it can be expressed by a depth‑four circuit of size n^{O(√n · log n)}. The √n factor arises from the balanced partition of the matrix rows and columns, while the log n factor reflects the overhead incurred when compressing each block to depth two. This bound is substantially stronger than the previously known exponential‑in‑√n bounds and provides a new quantitative handle on the complexity of the permanent under the polynomial‑size circuit assumption.

Beyond the permanent, the paper shows that the same technique yields especially efficient depth‑four representations for sums of products of sparse univariate polynomials. Such expressions appear frequently in algebraic algorithms, and the reduction to a small depth‑four circuit directly translates into more efficient deterministic polynomial identity testing (PIT) algorithms. In the black‑box model, the size reduction means that a deterministic tester can enumerate a much smaller set of evaluation points, thereby eliminating the need for randomness in many settings.

The authors also explore implications for Boolean circuit complexity. By applying their depth‑reduction to arithmetic circuits with polynomially bounded degree, they obtain a simple (though not optimal) transformation that reduces any such circuit to polylogarithmic depth while preserving polynomial size. This bridges a gap between arithmetic and Boolean models and suggests new avenues for proving lower bounds in restricted Boolean classes via arithmetic techniques.

In summary, the paper makes three major contributions: (1) it extends the depth‑four chasm to the regime of polynomial‑size circuits, delivering depth‑four circuits whose size is subexponential (often quasi‑polynomial) in the natural parameters; (2) it provides concrete applications to the permanent, sparse univariate polynomial sums, and deterministic PIT, thereby strengthening the link between depth‑four lower bounds and broader complexity‑theoretic questions; and (3) it offers a straightforward reduction from polynomial‑size, bounded‑degree arithmetic circuits to polylogarithmic depth, opening a new perspective on the relationship between circuit depth and size in both arithmetic and Boolean settings. These results deepen our understanding of why depth‑four circuits capture the essential difficulty of many algebraic problems and point toward promising directions for future research in circuit lower bounds and derandomization.