Theoretical Modeling and Simulation of Phase-Locked Loop (PLL) for Clock Data Recovery (CDR)

Modern communication and computer systems require rapid (Gbps), efficient and large bandwidth data transfers. Agressive scaling of digital integrated systems allow buses and communication controller circuits to be integrated with the microprocessor on the same chip. The Peripheral Component Interconnect Express (PCIe) protocol handles all communcation between the central processing unit (CPU) and hardware devices. PCIe buses require efficient clock data recovery circuits (CDR) to recover clock signals embedded in data during transmission. This paper describes the theoretical modeling and simulation of a phase-locked loop (PLL) used in a CDR circuit. A simple PLL architecture for a 5 GHz CDR circuit is proposed and elaborated in this work. Simulations were carried out using a Hardware Description Language, Verilog- AMS. The effect of jitter on the proposed design is also simulated and evaluated in this work. It was found that the proposed design is robust against both input and VCO jitter.

💡 Research Summary

The paper presents a comprehensive theoretical and simulation study of a phase‑locked loop (PLL) intended for clock‑data recovery (CDR) in high‑speed PCI Express (PCIe) links. Recognizing that modern CPUs and peripheral controllers are increasingly integrated and that PCIe Gen2 operates at 5 Gbps, the authors focus on recovering the embedded clock from a 50 MHz data‑stream reference and multiplying it to a 5 GHz recovered clock.

A compact PLL architecture is proposed, consisting of four main blocks: a phase detector (PD), an RLC low‑pass loop filter, a voltage‑controlled oscillator (VCO), and a feedback frequency divider. The PD compares the incoming 50 MHz clock with the divided feedback clock, producing a voltage proportional to the phase error (V_PD = K_PD·Δφ). The loop filter is a second‑order passive RLC network whose transfer function G(s) = 1/(s² + (R/L)s + 1/LC) provides the necessary low‑pass characteristic to suppress high‑frequency jitter while preserving loop stability. The VCO converts the filtered control voltage into a high‑frequency output according to ω_out = ω_in + K_VCO·V_cont, where K_VCO is the VCO gain. The divider reduces the 5 GHz VCO output by a factor of 100, feeding back a 50 MHz reference to the PD, thereby closing the loop.

The authors derive analytical expressions for each block, including the PD gain, filter component values, and VCO gain, and discuss how these parameters influence lock time, phase margin, and jitter attenuation. They then implement the entire system in Verilog‑AMS, a mixed‑signal hardware description language that allows concurrent modeling of analog behavior and digital control.

Two jitter scenarios are simulated. In the first, random phase jitter (Φ_in) is injected at the PD input. The simulation shows that the low‑pass filter effectively removes the high‑frequency component, and the output phase (Φ_out) remains clean, demonstrating the PLL’s ability to reject input jitter. In the second scenario, jitter is injected directly into the VCO (Φ_VCO) while the PD input is jitter‑free. Again, the loop quickly re‑locks, and the 5 GHz output remains a stable sinusoid, indicating robustness against VCO‑originated noise. Waveform plots (Figures 3‑10) illustrate these results.

The discussion highlights the simplicity and practicality of the design: a passive RLC filter and a basic PD/VCO pair can achieve GHz‑range CDR without complex digital signal processing. However, the authors acknowledge limitations: the second‑order filter may not provide optimal jitter suppression compared to higher‑order or active filters; the VCO model assumes linear voltage‑frequency behavior, ignoring temperature and process variations; and the noise model is limited to white Gaussian jitter, not covering realistic PCIe channel impairments such as common‑mode noise or power‑supply fluctuations.

In conclusion, the paper demonstrates that a straightforward analog PLL, modeled and verified with Verilog‑AMS, can generate a stable 5 GHz clock from a 50 MHz input and tolerate both input and VCO jitter. The work provides a solid foundation for integrating such PLL‑based CDR blocks into ASICs or SoCs targeting PCIe Gen2 and suggests future extensions involving higher‑order loop filters, digital loop control, and more comprehensive noise modeling to meet the demands of newer PCIe generations.