Designer-Driven Topology Optimization for Pipelined Analog to Digital Converters

In the digital world, RTL/logic synthesis is an indispensable tool for allowing system designers to explore high-level architecture, functional partitioning, and performance tradeoffs. Synthesis serves the role of completing a block to a level of concreteness that can be used to properly evaluate the merits of architecture-level tradeoff decisions. The questions we address in this paper are how recently introduced commercial-quality analog synthesis tools (e.g., [1] [2]) might play the same role in system-level analog design, and what a systematic methodology for this sort of design might look like. Two broad approaches have been suggested:

• Equation-based methods avoid simulation entirely, and strive to represent the design at all levels in an analytical form [3][4][5]. Convex models are the most successful here [4][5]. However, the method makes some serious tradeoffs emphasizing speed at the cost of design accuracy. • Hierarchical simulation-based methods use macromodels for the system-level design, and detailed models for the basic blocks, and then link these numerically. [6] is perhaps the most aggressive attempt in this direction. An alternative approach builds Pareto tradeoff curves for each basic block via detailed synthesis [7][8][9], then uses these to “parameterize” a system-level model. Both techniques are attractive, but not yet well-supported in commercial synthesis tools. We suggest a practical “hybrid” approach which integrates well with the current crop of commercial synthesis tools, and is moreover consistent with the style in which most analog system designers prefer to work. To make this concrete, we look at system-level architecture/topology power minimization for 40 MSPS pipelined ADCs in a 0.25µm 3.3V CMOS process with resolutions from 10 to 13 bits.

The pipelined ADC consists of a front-end sample and hold amplifier (S/H amplifier) and M pipelined stages and the number of bits to be converted in each stage (mi). One extra bit from each stage is used to implement digital correction logic. Designers have used a variety of configurations m1ˀm2m 3Ξ to design pipelined ADCs, starting from the classical 22 ˀ2Ξ or 1.5 bits per stage topology [5] to the recent 4ˀ2ˀ2Ξʳ [10]. The possible configuration sets {m1ˀm2ˀm3,Ξ} for a Kbit pipelined ADC is governed by

where K is the total effective number of bits over M stages with digital correction circuitry.

In this paper, candidate enumeration is used to explore all possible configurations such that m i Љ4 and m i Њm i+1 . The m i Љ4 constraint is due to closed-loop bandwidth concerns. The m i Њm i+1 constraint arises because of the area factor and is often used implicitly [5] [10]. Additionally, we only consider the first few stages such that the output resolution exceeds 7 bits. This is because ADC power is mainly consumed by the starting few bits [5]. These reduce the design space complexity to a manageable enumerated set of seven different candidates. Each candidate has several MDAC stages to be synthesized using method in section 3. The MDAC block-level specifications can be translated from the ADC system-level specifications and the value mi for the enumerated candidate

The proposed block-level synthesis design flow combines circuit analysis with simulation to reduce the design space and speed up transistor-level evaluation, enabling use of commercial cell-level synthesis tools. First, once the circuit topology of the MDAC block is decided, Driving-Point Impedances (DPI) / Signal-Flow Graphs (SFG) is used to draw the signal flow graph equivalent of the circuit. Second, the circuit symbolic transfer function is derived from the SFG by using Mason’s rule. With SFG and symbolic transfer function information, circuit characteristics such as poles/zeros, gain, phase-margin, are analyzed. The range of the design variables that define the design space and the design constraints are reduced using the DPI/SFG analysis results.

When circuits experience large dynamic swing, simulation-based evaluation produces trustworthy results within a short period of time. When circuit behavior is linear, transfer functions based on small signal parameters evaluate circuit performances accurately and efficiently. Combining these approaches has the advantage of high simulation accuracy and fast equation evaluation. Thus, evaluation of each candidate solution involves: 1) DC simulation to extract small signal values, 2) formulating the numerical transfer function, and using the toolkit for hybrid equation+simulation evaluation.

This evaluation procedure is performed automatically in each synthesis iteration.

Eleven MDACs used to enumerate the seven 13-bit ADC configurations were synthesized (using the Cadence NeoCircuit tool). Fig. 1 shows that the power of the first stage is mostly independent of the resolution of the first stage. Choosing 4-bits in the first stage, which minimizes the bits in the other stages, optimizes the power in the 13-bit case.

MDAC po

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