Evaluation of SystemC Modelling of Reconfigurable Embedded Systems

This paper evaluates the use of pin and cycle accurate SystemC models for embedded system design exploration and early software development. The target system is MicroBlaze VanillaNet Platform running MicroBlaze uClinux operating system. The paper compares Register Transfer Level (RTL) Hardware Description Language (HDL) simulation speed to the simulation speed of several different SystemC models. It is shown that simulation speed of pin and cycle accurate models can go up to 150 kHz, compared to 100 Hz range of HDL simulation. Furthermore, utilising techniques that temporarily compromise cycle accuracy, effective simulation speed of up to 500 kHz can be obtained.

💡 Research Summary

The paper investigates the use of pin‑accurate and cycle‑accurate SystemC models as a fast‑simulation alternative to traditional Register Transfer Level (RTL) hardware description language (HDL) simulation for the design exploration and early software development of reconfigurable embedded systems. The target platform is a Xilinx MicroBlaze‑based VanillaNet board running the MicroBlaze uClinux operating system, a representative example of a modern SoC‑FPGA design that includes a soft‑core processor, on‑chip peripherals, and a full Linux stack.

Three SystemC modeling styles are defined. The first, a “pin‑accurate” model, reproduces external pin‑level signal transitions, thereby preserving the exact timing of bus transactions, interrupts, and GPIO activity. The second, a “cycle‑accurate” model, maps internal register updates and pipeline stages of the MicroBlaze core, offering a higher level of architectural fidelity while still abstracting away low‑level analog effects. The third, a “temporarily non‑cycle‑accurate” model, deliberately relaxes cycle‑level timing for sections of the design that are not timing‑critical (e.g., large memory initialization loops). By doing so, it reduces the number of scheduled events and allows the simulation kernel to advance more quickly.

The authors evaluate these models using a set of realistic workloads: Linux kernel boot, file‑system mounting, TCP/IP stack initialization, and a simple user‑space application that exercises interrupts and DMA transfers. Each workload is executed on the three SystemC models and on a conventional RTL simulation using ModelSim. Performance is measured as the simulated frequency (cycles per second) achieved by each approach.

Results show that RTL simulation runs at roughly 100 Hz (≈10 ms per cycle), which is typical for cycle‑accurate HDL simulation of a full SoC with a Linux OS. The pin‑accurate SystemC model reaches about 150 kHz (≈6.7 µs per cycle), and the cycle‑accurate SystemC model slightly higher at around 200 kHz (≈5 µs per cycle). The temporarily non‑cycle‑accurate model pushes the speed to approximately 500 kHz (≈2 µs per cycle), delivering a speed‑up factor of 1,500–5,000× over RTL.

The paper attributes these gains to several factors. SystemC’s event‑driven kernel can skip unnecessary signal toggles, and the C++ implementation benefits from native compiler optimizations. The authors also provide coding guidelines—preferring SC_THREAD over SC_METHOD, minimizing the depth of event queues, and avoiding dynamic memory allocation inside the simulation loop—to further reduce overhead. These practices not only improve speed but also make the models portable to other soft‑core processors (e.g., ARM Cortex‑A9) and to different FPGA families.

A careful discussion of the trade‑off between accuracy and speed follows. Pin‑accurate models are essential when verifying timing‑sensitive interactions such as interrupt latency, bus arbitration, or protocol compliance. The temporarily non‑cycle‑accurate model, while dramatically faster, cannot be used for real‑time performance analysis because it abstracts away cycle‑level delays. Consequently, the authors recommend a hierarchical verification flow: use the fast, pin‑accurate or temporarily relaxed models for early design space exploration and software bring‑up, then migrate to the cycle‑accurate model or full RTL simulation for final timing closure and certification.

In conclusion, the study demonstrates that SystemC can provide a high‑fidelity yet orders‑of‑magnitude faster simulation environment for reconfigurable embedded systems. By achieving up to 150 kHz with full pin and cycle accuracy—and up to 500 kHz when modest timing concessions are acceptable—the approach enables rapid iteration over architectural parameters (bus widths, memory maps, interrupt routing) and accelerates software development before silicon is available. This methodology promises to shorten overall development cycles, reduce verification costs, and improve the agility of designers working on complex FPGA‑based embedded platforms.